Inventor · disambiguated record
Jensen Tjeng
Also filed as: TJENG JENSEN
9 granted patents·71 citations·filing 2003–2012
85Inventor score
Technology areasG06F
Top patents by PatentIndex Score
9 records- 0186US7096345B1Data processing system with bypass reorder buffer having non-bypassable locations and combined load/store arithmetic logic unit and processing method thereofMARVELL INT LTD·Filed 2003·Granted Aug 22, 2006·47 cites·58 claims
- 0283US8074056B1Variable length pipeline processor architectureCHEN HONG-YI·Filed 2005·Granted Dec 6, 2011·13 cites·30 claims
- 0371US8526257B2Processor with memory delayed bit line prechargingMARVELL WORLD TRADE LTD·Filed 2012·Granted Sep 3, 2013·2 cites·20 claims
- 0470US8295110B2Processor instruction cache with dual-read modesSUTARDJA SEHAT·Filed 2011·Granted Oct 23, 2012·2 cites·20 claims
- 0570US7730285B1Data processing system with partial bypass reorder buffer and combined load/store arithmetic logic unit and processing method thereofMARVELL INT LTD·Filed 2006·Granted Jun 1, 2010·4 cites·32 claims
- 0667US8027218B2Processor instruction cache with dual-read modesMARVELL WORLD TRADE LTD·Filed 2008·Granted Sep 27, 2011·3 cites·52 claims
- 0751US7787324B2Processor instruction cache with dual-read modesMARVELL WORLD TRADE LTD·Filed 2007·Granted Aug 31, 2010·0 cites·37 claims
- 0849US8909903B1Providing data to registers between execution stagesCHEN HONG-YI·Filed 2011·Granted Dec 9, 2014·0 cites·28 claims
- 0948US8089823B2Processor instruction cache with dual-read modesSUTARDJA SEHAT·Filed 2010·Granted Jan 3, 2012·0 cites·19 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →