Inventor · disambiguated record
Jesse Wang
Also filed as: WANG JESSE · WANG JESSE S · WANG JESSE SAN-JEY
9 granted patents·5 pending applications·5 citations·filing 2013–2025
77Inventor score
Files withNVIDIA CORP14
Top patents by PatentIndex Score
14 records- 0173US9418730B2Handshaking sense amplifierNVIDIA CORP·Filed 2013·Granted Aug 16, 2016·5 cites·20 claims
- 0272US2025252982A1Contention-free dual-voltage logic cellNVIDIA CORP·Filed 2025·Application pending·0 cites
- 0367US12322471B2Contention-free dual-voltage logic cellNVIDIA CORP·Filed 2023·Granted Jun 3, 2025·0 cites·20 claims
- 0462US12131775B2Keeper-free volatile memory systemNVIDIA CORP·Filed 2022·Granted Oct 29, 2024·0 cites·16 claims
- 0558US12395175B2Level-shifter having a wide operating range, a fast output fall delay and improved rise timeNVIDIA CORP·Filed 2023·Granted Aug 19, 2025·0 cites·23 claims
- 0656US12315589B2Multi-voltage RAM used to cross clock and voltage domainsNVIDIA CORP·Filed 2023·Granted May 27, 2025·0 cites·22 claims
- 0755US11804262B2Area efficient memory cell read disturb mitigationNVIDIA CORP·Filed 2021·Granted Oct 31, 2023·0 cites·16 claims
- 0851US11854660B2Slew signal shaper circuit using two signal pathsNVIDIA CORP·Filed 2021·Granted Dec 26, 2023·0 cites·13 claims
- 0950US10009027B2Three state latchNVIDIA CORP·Filed 2017·Granted Jun 26, 2018·0 cites·22 claims
- 1048US2025226014A1Output latch and amplifierNVIDIA CORP·Filed 2024·Application pending·0 cites
- 1147US2025201301A1Capacitive noise compensation for a read bitline in a machine memoryNVIDIA CORP·Filed 2023·Application pending·0 cites
- 1243US10141930B2Three state latchNVIDIA CORP·Filed 2013·Granted Nov 27, 2018·0 cites·20 claims
- 1343US2024161815A1Dual port dual power rail memory architectureNVIDIA CORP·Filed 2022·Application pending·0 cites
- 1433US2014355362A1Pipelined one cycle throughput for single-port 6t ramNVIDIA CORP·Filed 2013·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →