Inventor · disambiguated record
Jennifer Wong
Also filed as: WONG JENNIFER · WONG JENNIFER K
47 granted patents·3,671 citations·filing 1995–2011
99Inventor score
Top patents by PatentIndex Score
47 records- 0199US6480954B2Method of time multiplexing a programmable logic deviceXILINX INC·Filed 2001·Granted Nov 12, 2002·318 cites·13 claims
- 0299US5629637AMethod of time multiplexing a programmable logic deviceXILINX INC·Filed 1995·Granted May 13, 1997·295 cites·14 claims
- 0399US5600263AConfiguration modes for a time multiplexed programmable logic deviceXILINX INC·Filed 1995·Granted Feb 4, 1997·285 cites·13 claims
- 0498US7472155B2Programmable logic device with cascading DSP slicesXILINX INC·Filed 2004·Granted Dec 30, 2008·111 cites·44 claims
- 0598US5978260AMethod of time multiplexing a programmable logic deviceXILINX INC·Filed 1998·Granted Nov 2, 1999·164 cites·56 claims
- 0698US5778439AProgrammable logic device with hierarchical confiquration and state storageXILINX INC·Filed 1995·Granted Jul 7, 1998·226 cites·20 claims
- 0798US5646545ATime multiplexed programmable logic deviceXILINX INC·Filed 1995·Granted Jul 8, 1997·475 cites·65 claims
- 0897US5583450ASequencer for a time multiplexed programmable logic deviceXILINX INC·Filed 1995·Granted Dec 10, 1996·182 cites·27 claims
- 0996US6263430B1Method of time multiplexing a programmable logic deviceXILINX INC·Filed 1999·Granted Jul 17, 2001·96 cites·8 claims
- 1095US6366117B1Nonvolatile/battery-backed key in PLDXILINX INC·Filed 2000·Granted Apr 2, 2002·126 cites·7 claims
- 1194US6931543B1Programmable logic device with decryption algorithm and decryption keyXILINX INC·Filed 2000·Granted Aug 16, 2005·114 cites·27 claims
- 1294US6441641B1Programmable logic device with partial battery backupXILINX INC·Filed 2000·Granted Aug 27, 2002·113 cites·6 claims
- 1392US7567997B2Applications of cascading DSP slicesXILINX INC·Filed 2004·Granted Jul 28, 2009·71 cites·16 claims
- 1492US5933025ALow voltage interface circuit with a high voltage toleranceXILINX INC·Filed 1997·Granted Aug 3, 1999·102 cites·7 claims
- 1591US7882165B2Digital signal processing element having an arithmetic logic unitXILINX INC·Filed 2006·Granted Feb 1, 2011·25 cites·19 claims
- 1691US7467175B2Programmable logic device with pipelined DSP slicesXILINX INC·Filed 2004·Granted Dec 16, 2008·45 cites·33 claims
- 1790US7480690B2Arithmetic circuit with multiplexed addend inputsXILINX INC·Filed 2004·Granted Jan 20, 2009·61 cites·29 claims
- 1889US7117373B1Bitstream for configuring a PLD with encrypted design dataXILINX INC·Filed 2000·Granted Oct 3, 2006·65 cites·20 claims
- 1988US6981153B1Programmable logic device with method of preventing readbackXILINX INC·Filed 2000·Granted Dec 27, 2005·53 cites·7 claims
- 2088US6957340B1Encryption key for multi-key encryption in programmable logic deviceXILINX INC·Filed 2000·Granted Oct 18, 2005·54 cites·25 claims
- 2188US5959881AProgrammable logic device including configuration data or user data memory slicesXILINX INC·Filed 1997·Granted Sep 28, 1999·100 cites·7 claims
- 2287US7216277B1Self-repairing redundancy for memory blocks in programmable logic devicesXILINX INC·Filed 2003·Granted May 8, 2007·50 cites·42 claims
- 2387US7117372B1Programmable logic device with decryption and structure for preventing design relocationXILINX INC·Filed 2000·Granted Oct 3, 2006·56 cites·19 claims
- 2487US6803786B1Structures and methods providing columns of tightly coupled processor and RAM blocks within an array of logic blocksXILINX INC·Filed 2003·Granted Oct 12, 2004·26 cites·20 claims
- 2585US7467177B2Mathematical circuit with dynamic roundingXILINX INC·Filed 2004·Granted Dec 16, 2008·43 cites·30 claims
- 2685US6204695B1Clock-gating circuit for reducing power consumptionXILINX INC·Filed 1999·Granted Mar 20, 2001·122 cites·8 claims
- 2784US7870182B2Digital signal processing circuit having an adder circuit with carry-outsXILINX INC·Filed 2006·Granted Jan 11, 2011·21 cites·20 claims
- 2882US7840630B2Arithmetic logic unit circuitXILINX INC·Filed 2006·Granted Nov 23, 2010·17 cites·20 claims
- 2982US5784313AProgrammable logic device including configuration data or user data memory slicesXILINX INC·Filed 1995·Granted Jul 21, 1998·68 cites·9 claims
- 3080US7865542B2Digital signal processing block having a wide multiplexerXILINX INC·Filed 2006·Granted Jan 4, 2011·16 cites·16 claims
- 3177US7853632B2Architectural floorplan for a digital signal processing circuitXILINX INC·Filed 2006·Granted Dec 14, 2010·12 cites·20 claims
- 3277US7849119B2Digital signal processing circuit having a pattern detector circuitXILINX INC·Filed 2006·Granted Dec 7, 2010·12 cites·19 claims
- 3375US7860915B2Digital signal processing circuit having a pattern circuit for determining termination conditionsXILINX INC·Filed 2006·Granted Dec 28, 2010·11 cites·16 claims
- 3475US7844653B2Digital signal processing circuit having a pre-adder circuitXILINX INC·Filed 2006·Granted Nov 30, 2010·11 cites·18 claims
- 3574US7853634B2Digital signal processing circuit having a SIMD circuitXILINX INC·Filed 2006·Granted Dec 14, 2010·10 cites·20 claims
- 3674US7853636B2Digital signal processing circuit having a pattern detector circuit for convergent roundingXILINX INC·Filed 2006·Granted Dec 14, 2010·10 cites·20 claims
- 3774US7181718B1Structures and methods providing columns of tightly coupled processor and RAM blocks within an array of logic blocksXILINX INC·Filed 2004·Granted Feb 20, 2007·13 cites·29 claims
- 3873US7286382B1Segmented dataline scheme in a memory with enhanced full fault coverage memory cell testabilityXILINX INC·Filed 2006·Granted Oct 23, 2007·7 cites·5 claims
- 3972US7417918B1Method and apparatus for configuring the operating speed of a programmable logic device through a self-timed reference circuitXILINX INC·Filed 2004·Granted Aug 26, 2008·18 cites·13 claims
- 4071US7314174B1Method and system for configuring an integrated circuitXILINX INC·Filed 2004·Granted Jan 1, 2008·14 cites·16 claims
- 4170US7840627B2Digital signal processing circuit having input register blocksXILINX INC·Filed 2006·Granted Nov 23, 2010·8 cites·19 claims
- 4266US8495122B2Programmable device with dynamic DSP architectureSIMKINS JAMES M·Filed 2004·Granted Jul 23, 2013·12 cites·16 claims
- 4360US7142442B1Segmented dataline scheme in a memory with enhanced full fault coverage memory cell testabilityXILINX INC·Filed 2004·Granted Nov 28, 2006·9 cites·39 claims
- 4459US8601351B2BCH decoding with multiple sigma polynomial calculation algorithmsWONG JENNIFER K·Filed 2011·Granted Dec 3, 2013·3 cites·23 claims
- 4553US7038519B1Digital clock manager having cascade voltage switch logic clock pathsXILINX INC·Filed 2004·Granted May 2, 2006·5 cites·11 claims
- 4651US6353341B1Method and apparatus for discriminating against signal interferenceXILINX INC·Filed 1999·Granted Mar 5, 2002·15 cites·4 claims
- 4740US6946874B1Structures and methods providing columns of tightly coupled processor and RAM blocks within an array of logic blocksXILINX INC·Filed 2004·Granted Sep 20, 2005·1 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →