Inventor · disambiguated record
Jihong Choi
Also filed as: CHOI JIHONG
10 granted patents·15 pending applications·30 citations·filing 2009–2024
85Inventor score
Top patents by PatentIndex Score
25 records- 0187US8980708B2Complementary back end of line (BEOL) capacitorQUALCOMM INC·Filed 2013·Granted Mar 17, 2015·8 cites·8 claims
- 0283US12218041B2Integrated circuit (IC) packages employing a capacitor-embedded, redistribution layer (RDL) substrate for interfacing an IC chip(s) to a package substrate, and related methodsQUALCOMM INC·Filed 2021·Granted Feb 4, 2025·1 cites·20 claims
- 0383US10833017B2Contact for semiconductor deviceQUALCOMM INC·Filed 2016·Granted Nov 10, 2020·4 cites·12 claims
- 0481US9269492B2Bone frame, low resistance via coupled metal oxide-metal (MOM) orthogonal finger capacitorQUALCOMM INC·Filed 2013·Granted Feb 23, 2016·6 cites·22 claims
- 0580US9252104B2Complementary back end of line (BEOL) capacitorQUALCOMM INC·Filed 2014·Granted Feb 2, 2016·4 cites·12 claims
- 0680US8105942B2CMP-first damascene process schemeCHOI JIHONG·Filed 2010·Granted Jan 31, 2012·6 cites·14 claims
- 0776US2025118645A1Integrated circuit (ic) packages employing a capacitor-embedded, redistribution layer (rdl) substrate for interfacing an ic chip(s) to a package substrate, and related methodsQUALCOMM INC·Filed 2024·Application pending·0 cites
- 0863US2025380406A1Vertical bank redundancy in three-dimensional stacked dynamic random-access memory (dram) for improved yieldQUALCOMM INC·Filed 2024·Application pending·0 cites
- 0963US2025380431A1High-bandwidth three-dimensional stacked memory with a base die enabling compute logic without memory power grid restrictionsQUALCOMM INC·Filed 2024·Application pending·0 cites
- 1062US2025391739A1Dual-liner through-silicon via (tsv) for power and signal transmissionQUALCOMM INC·Filed 2024·Application pending·0 cites
- 1161US2025385222A1High-bandwidth integrated circuit packaging of memory and logicQUALCOMM INC·Filed 2024·Application pending·0 cites
- 1261US2025379188A1High-bandwidth memory (hbm) package-on-package (pop) dynamic random-access memory (dram) with semiconductor pillarsQUALCOMM INC·Filed 2024·Application pending·0 cites
- 1361US2025385209A1Bumpless fan-out wafer-level integrated circuit package including memory and logicQUALCOMM INC·Filed 2024·Application pending·0 cites
- 1461US2025386517A1High bandwidth small form factor 3d integrated circuit package including memory and logicQUALCOMM INC·Filed 2024·Application pending·0 cites
- 1560US2025300068A1Power/thermal via for three-dimensional (3d) chip stackingQUALCOMM INC·Filed 2024·Application pending·0 cites
- 1658US8241927B2Methods relating to capacitive monitoring of layer characteristics during back end-of the-line processingCHOI JIHONG·Filed 2009·Granted Aug 14, 2012·1 cites·20 claims
- 1756US11973019B2Deep trench capacitors in an inter-layer medium on an interconnect layer of an integrated circuit die and related methodsQUALCOMM INC·Filed 2021·Granted Apr 30, 2024·0 cites·22 claims
- 1856US2025015047A1Single-step via-last process for multi-stack wafersQUALCOMM INC·Filed 2023·Application pending·0 cites
- 1953US2024079352A1Integrated circuit (ic) packages employing capacitor interposer substrate with aligned external interconnects, and related fabrication methodsQUALCOMM INC·Filed 2022·Application pending·0 cites
- 2048US9245971B2Semiconductor device having high mobility channelQUALCOMM INC·Filed 2013·Granted Jan 26, 2016·0 cites·45 claims
- 2142US2014203404A1Spiral metal-on-metal (smom) capacitors, and related systems and methodsQUALCOMM INC·Filed 2013·Application pending·0 cites
- 2241US2013320494A1Metal finger capacitors with hybrid metal finger orientations in stack with unidirectional metal layersQUALCOMM INC·Filed 2012·Application pending·0 cites
- 2340US2014197519A1Mim capacitor and mim capacitor fabrication for semiconductor devicesQUALCOMM INC·Filed 2013·Application pending·0 cites
- 2440US2014197520A1Resistor and resistor fabrication for semiconductor devicesQUALCOMM INC·Filed 2013·Application pending·0 cites
- 2537US9941156B2Systems and methods to reduce parasitic capacitanceQUALCOMM INC·Filed 2015·Granted Apr 10, 2018·0 cites·16 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →