Inventor · disambiguated record
Jieying Kong
Also filed as: Kong Jieying
8 granted patents·21 pending applications·2 citations·filing 2019–2024
73Inventor score
Top patents by PatentIndex Score
29 records- 0177US12442979B2Optical waveguide formed within in a glass layerINTEL CORP·Filed 2021·Granted Oct 14, 2025·1 cites·25 claims
- 0268US11780210B2Glass dielectric layer with patterningINTEL CORP·Filed 2019·Granted Oct 10, 2023·1 cites·9 claims
- 0366US2023405976A1Glass dielectric layer with patterningINTEL CORP·Filed 2023·Application pending·0 cites
- 0455US2025379163A1Microelectronic assemblies having a glass layer substrate with integrated capacitorsINTEL CORP·Filed 2024·Application pending·0 cites
- 0554US2025112138A1Microelectronic structures including glass substrates with dielectric based liner materials.INTEL CORP·Filed 2023·Application pending·0 cites
- 0654US2025309148A1Substrate with component embedded in a blind cavityINTEL CORP·Filed 2024·Application pending·0 cites
- 0753US2024112999A1Layered glass assembly with pre-patterned electrically conductive interconnectsINTEL CORP·Filed 2022·Application pending·0 cites
- 0853US2025300062A1Integrated circuit package comprising hollow filler-based build-up materialINTEL CORP·Filed 2024·Application pending·0 cites
- 0953US2025192059A1Embedded bridge with through silicon via bonding architecturesINTEL CORP·Filed 2023·Application pending·0 cites
- 1053US2025112136A1Glass core protection using peripheral buffer layersINTEL CORP·Filed 2023·Application pending·0 cites
- 1152US12512397B2Substrates having adhesion promotor layers and related methodsTHE INTEL CORP·Filed 2022·Granted Dec 30, 2025·0 cites·20 claims
- 1252US2025112163A1Through-glass via liners for integrated circuit device packagesINTEL CORP·Filed 2023·Application pending·0 cites
- 1351US12125777B2Minimizing package impedance discontinuity through dielectric structure optimizationsINTEL CORP·Filed 2019·Granted Oct 22, 2024·0 cites·21 claims
- 1451US2024217216A1Ultrathin laminated glass and glass stiffeners for coreless packagesINTEL CORP·Filed 2022·Application pending·0 cites
- 1551US2023420348A1Sinx adhesion promoter with adhesion hole features in packaging substrate for reliability performance enhancementINTEL CORP·Filed 2022·Application pending·0 cites
- 1650US11574862B2Optimal signal routing performance through dielectric material configuration designs in package substrateINTEL CORP·Filed 2019·Granted Feb 7, 2023·0 cites·19 claims
- 1750US2025006623A1Forming porous dielectric structures with spatially-controlled porosityINTEL CORP·Filed 2023·Application pending·0 cites
- 1850US2025112140A1Stress mitigation architectures for glass core substratesINTEL CORP·Filed 2023·Application pending·0 cites
- 1949US12191240B2Hybrid glass core for wafer level and panel level packaging applicationsINTEL CORP·Filed 2019·Granted Jan 7, 2025·0 cites·24 claims
- 2048US12033930B2Selectively roughened copper architectures for low insertion loss conductive featuresINTEL CORP·Filed 2020·Granted Jul 9, 2024·0 cites·18 claims
- 2147US2024096561A1Thin film capacitorsINTEL CORP·Filed 2022·Application pending·0 cites
- 2246US2023207503A1Stress arrest lip on copper pad for low roughness copperINTEL CORP·Filed 2021·Application pending·0 cites
- 2346US2024222089A1Enhanced dry desmear equipment with protective film peeling capability for integrated circuitsINTEL CORP·Filed 2022·Application pending·0 cites
- 2446US2023420353A1Asymmetrical dielectric-to-metal adhesion architecture for electronic packagesINTEL CORP·Filed 2022·Application pending·0 cites
- 2546US2023089928A1Semiconductor devices having hollow filler materialsLIN ZIYIN·Filed 2021·Application pending·0 cites
- 2644US2023090188A1Multi layer package substrate having different dielectric materials for metal layers with different circuit structuresINTEL CORP·Filed 2021·Application pending·0 cites
- 2744US2024006296A1Build up material architecture for microelectronic package deviceINTEL CORP·Filed 2022·Application pending·0 cites
- 2843US11348865B2Electronic device including a substrate having interconnectsINTEL CORP·Filed 2019·Granted May 31, 2022·0 cites·22 claims
- 2942US2023086881A1Double-sided glass substrate with a hybrid bonded photonic integrated circuitINTEL CORP·Filed 2021·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →