Inventor · disambiguated record
Jian Xun Li
Also filed as: LI JIAN X · LI JIAN XUN
16 granted patents·2 pending applications·303 citations·filing 1997–2005
94Inventor score
Top patents by PatentIndex Score
18 records- 0192US6709918B1Method for making a metal-insulator-metal (MIM) capacitor and metal resistor for a copper back-end-of-line (BEOL) technologyCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Mar 23, 2004·87 cites·30 claims
- 0276US5930627AProcess improvements in self-aligned polysilicon MOSFET technology using silicon oxynitrideCHARTERED SEMICONDUCTOR MFG·Filed 1997·Granted Jul 27, 1999·44 cites·18 claims
- 0371US7022578B2Heterojunction bipolar transistor using reverse emitter windowCHARTERED SEMICONDUCTOR MFG·Filed 2003·Granted Apr 4, 2006·18 cites·10 claims
- 0466US6410394B1Method for forming self-aligned channel implants using a gate poly reverse maskCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Jun 25, 2002·21 cites·8 claims
- 0565US5948701ASelf-aligned contact (SAC) etching using polymer-building chemistryCHARTERED SEMICONDUCTOR MFG·Filed 1997·Granted Sep 7, 1999·32 cites·10 claims
- 0661US6524963B1Method to improve etching of organic-based, low dielectric constant materialsCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Feb 25, 2003·24 cites·29 claims
- 0760US6489191B2Method for forming self-aligned channel implants using a gate poly reverse maskCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Dec 3, 2002·8 cites·10 claims
- 0857US6972237B2Lateral heterojunction bipolar transistor and method of manufacture using selective epitaxial growthCHARTERED SEMICONDUCTOR MFG·Filed 2003·Granted Dec 6, 2005·7 cites·32 claims
- 0955US6534393B1Method for fabricating local metal interconnections with low contact resistance and gate electrodes with improved electrical conductivityCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Mar 18, 2003·19 cites·30 claims
- 1050US6140206AMethod to form shallow trench isolation structuresCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Oct 31, 2000·17 cites·20 claims
- 1149US7049201B2Method and apparatus for a heterojunction bipolar transistor using self-aligned epitaxyCHARTERED SEMIONDUCTOR MFG LTD·Filed 2003·Granted May 23, 2006·6 cites·18 claims
- 1247US7238971B2Self-aligned lateral heterojunction bipolar transistorCHARTERED SEMICONDUCTOR MFG·Filed 2005·Granted Jul 3, 2007·0 cites·10 claims
- 1345US6924202B2Heterojunction bipolar transistor with self-aligned emitter and sidewall base contactCHARTERED SEMICONDUCTOR MFG·Filed 2003·Granted Aug 2, 2005·2 cites·20 claims
- 1445US5792692AMethod of fabricating a twin hammer tree shaped capacitor structure for a dram deviceCHARTERED SEMICONDUCTOR MFG·Filed 1997·Granted Aug 11, 1998·12 cites·23 claims
- 1543US6908824B2Self-aligned lateral heterojunction bipolar transistorCHARTERED SEMICONDUCTOR MFG·Filed 2003·Granted Jun 21, 2005·1 cites·10 claims
- 1636US2003143828A1Novel method of fabricating metallic local interconnections that also improves transistor performanceCHARTERED SEMICONDUCTOR MFG·Filed 2003·Application pending·0 cites
- 1736US2005145953A1Heterojunction BiCMOS integrated circuits and method thereforCHARTERED SEMICONDUCTOR MFG·Filed 2004·Application pending·0 cites
- 1834US6395631B1Low dielectric constant dielectric layer fabrication method employing hard mask layer delaminationCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted May 28, 2002·5 cites·9 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →