Inventor · disambiguated record
Jiun-Wei Lu
Also filed as: LU JIUN-WEI
5 granted patents·1 pending application·3 citations·filing 2011–2025
66Inventor score
Top patents by PatentIndex Score
6 records- 0194US11935830B2Integrated circuit with frontside and backside conductive layers and exposed backside substrateTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Mar 19, 2024·2 cites·20 claims
- 0283US2025329639A1Integrated circuit with frontside and backside conductive layers and exposed backside substrateTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 0381US12456679B2Backside conductive segments cover a first active region and define an opening above a second active regionTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Granted Oct 28, 2025·0 cites·20 claims
- 0458US11909396B2Integrated circuit including back side conductive lines for clock signalsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Feb 20, 2024·0 cites·20 claims
- 0555US8823621B2Buffer and display system utilizing the sameCHU TING-YAO·Filed 2011·Granted Sep 2, 2014·1 cites·10 claims
- 0652US11437998B2Integrated circuit including back side conductive lines for clock signalsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Sep 6, 2022·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →