Inventor · disambiguated record
Jiajin Tu
Also filed as: TU JIAJIN
8 granted patents·3 pending applications·15 citations·filing 2010–2022
79Inventor score
Top patents by PatentIndex Score
11 records- 0190US11334648B2Matrix multiplierHUAWEI TECH CO LTD·Filed 2020·Granted May 17, 2022·3 cites·10 claims
- 0276US9489204B2Method and apparatus for precalculating a direct branch partial target address during a misprediction correction processQUALCOMM INC·Filed 2013·Granted Nov 8, 2016·4 cites·30 claims
- 0374US9122486B2Bimodal branch predictor encoded in a branch instructionVENKUMAHANTI SURESH K·Filed 2010·Granted Sep 1, 2015·5 cites·22 claims
- 0467US9804969B2Speculative addressing using a virtual address-to-physical address page crossing bufferQUALCOMM INC·Filed 2012·Granted Oct 31, 2017·2 cites·24 claims
- 0565US11934481B2Matrix multiplierHUAWEI TECH CO LTD·Filed 2022·Granted Mar 19, 2024·0 cites·18 claims
- 0664US9858201B2Selective translation lookaside buffer search and page faultQUALCOMM INC·Filed 2015·Granted Jan 2, 2018·1 cites·24 claims
- 0746US11823303B2Data processing method and apparatusHUAWEI TECH CO LTD·Filed 2020·Granted Nov 21, 2023·0 cites·12 claims
- 0846US2020026746A1Matrix and Vector Multiplication Operation Method and ApparatusHUAWEI TECH CO LTD·Filed 2019·Application pending·0 cites
- 0943US2023169621A1Compute shader with load tileHUAWEI TECH CO LTD·Filed 2021·Application pending·0 cites
- 1042US9658793B2Adaptive mode translation lookaside buffer search and access faultQUALCOMM INC·Filed 2015·Granted May 23, 2017·0 cites·32 claims
- 1132US2017090922A1Efficient Instruction Pair for Central Processing Unit (CPU) Instruction DesignFUTUREWEI TECHNOLOGIES INC·Filed 2015·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →