Inventor · disambiguated record
Jianyong Xie
Also filed as: XIE JIANYONG
29 granted patents·8 pending applications·64 citations·filing 2011–2024
95Inventor score
Top patents by PatentIndex Score
37 records- 0198US11621227B2Power delivery for embedded bridge die utilizing trench structuresINTEL CORP·Filed 2021·Granted Apr 4, 2023·6 cites·25 claims
- 0297US11837549B2Power delivery for embedded bridge die utilizing trench structuresINTEL CORP·Filed 2022·Granted Dec 5, 2023·3 cites·20 claims
- 0397US11817391B2Power delivery for embedded bridge die utilizing trench structuresINTEL CORP·Filed 2023·Granted Nov 14, 2023·3 cites·20 claims
- 0497US10847467B2Power-delivery methods for embedded multi-die interconnect bridges and methods of assembling sameINTEL CORP·Filed 2019·Granted Nov 24, 2020·21 cites·20 claims
- 0596US12062616B2Power delivery for embedded bridge die utilizing trench structuresINTEL CORP·Filed 2023·Granted Aug 13, 2024·2 cites·20 claims
- 0693US11222848B2Power delivery for embedded bridge die utilizing trench structuresINTEL CORP·Filed 2017·Granted Jan 11, 2022·6 cites·25 claims
- 0792US10950550B2Semiconductor package with through bridge die connectionsINTEL CORP·Filed 2015·Granted Mar 16, 2021·10 cites·22 claims
- 0888US11728294B2Capacitor die embedded in package substrate for providing capacitance to surface mounted dieINTEL CORP·Filed 2021·Granted Aug 15, 2023·1 cites·22 claims
- 0986US10490503B2Power-delivery methods for embedded multi-die interconnect bridges and methods of assembling sameINTEL CORP·Filed 2018·Granted Nov 26, 2019·4 cites·26 claims
- 1084US2024321785A1Capacitor die embedded in package substrate for providing capacitance to surface mounted dieINTEL CORP·Filed 2024·Application pending·0 cites
- 1182US12046568B2Capacitor die embedded in package substrate for providing capacitance to surface mounted dieINTEL CORP·Filed 2023·Granted Jul 23, 2024·0 cites·20 claims
- 1279US2025112209A1Semiconductor packages with chiplets coupled to a memory deviceINTEL CORP·Filed 2024·Application pending·0 cites
- 1377US11276635B2Horizontal pitch translation using embedded bridge diesINTEL CORP·Filed 2017·Granted Mar 15, 2022·2 cites·22 claims
- 1474US12205924B2Semiconductor packages with chiplets coupled to a memory deviceINTEL CORP·Filed 2023·Granted Jan 21, 2025·0 cites·20 claims
- 1571US11610862B2Semiconductor packages with chiplets coupled to a memory deviceINTEL CORP·Filed 2018·Granted Mar 21, 2023·1 cites·24 claims
- 1671US10651117B2Low-inductance current paths for on-package power distributions and methods of assembling sameINTEL CORP·Filed 2018·Granted May 12, 2020·1 cites·18 claims
- 1770US11621223B2Interconnect hub for diesINTEL CORP·Filed 2019·Granted Apr 4, 2023·1 cites·20 claims
- 1870US2025125268A1Emib architecture with dedicated metal layers for improving power deliveryINTEL CORP·Filed 2024·Application pending·0 cites
- 1969US11887932B2Dielectric-filled trench isolation of viasINTEL CORP·Filed 2022·Granted Jan 30, 2024·0 cites·10 claims
- 2068US11694952B2Horizontal pitch translation using embedded bridge diesINTEL CORP·Filed 2022·Granted Jul 4, 2023·0 cites·25 claims
- 2166US11456281B2Architecture and processes to enable high capacity memory packages through memory die stackingINTEL CORP·Filed 2018·Granted Sep 27, 2022·1 cites·16 claims
- 2264US9037446B2Electrical-thermal co-simulation with joule heating and convection effects for 3D systemsXIE JIANYONG·Filed 2011·Granted May 19, 2015·2 cites·17 claims
- 2362US11222837B2Low-inductance current paths for on-package power distributions and methods of assembling sameINTEL CORP·Filed 2020·Granted Jan 11, 2022·0 cites·16 claims
- 2459US12218063B2EMIB architecture with dedicated metal layers for improving power deliveryINTEL CORP·Filed 2020·Granted Feb 4, 2025·0 cites·23 claims
- 2559US11195805B2Capacitor die embedded in package substrate for providing capacitance to surface mounted dieINTEL CORP·Filed 2018·Granted Dec 7, 2021·0 cites·20 claims
- 2655US11114394B2Signal routing carrierINTEL CORP·Filed 2019·Granted Sep 7, 2021·0 cites·10 claims
- 2754US11296031B2Dielectric-filled trench isolation of viasINTEL CORP·Filed 2018·Granted Apr 5, 2022·0 cites·7 claims
- 2851US2024006286A1Layer selection for routing high-speed signals in substratesINTEL CORP·Filed 2022·Application pending·0 cites
- 2950US12057413B2Package design scheme for enabling high-speed low-loss signaling and mitigation of manufacturing risk and costINTEL CORP·Filed 2019·Granted Aug 6, 2024·0 cites·21 claims
- 3050US2023299044A1Passive electrical components in mold metal layers of a multi-die complexINTEL CORP·Filed 2022·Application pending·0 cites
- 3148US11462521B2Multilevel die complex with integrated discrete passive componentsINTEL CORP·Filed 2018·Granted Oct 4, 2022·0 cites·20 claims
- 3248US11387187B2Embedded very high density (VHD) layerINTEL CORP·Filed 2018·Granted Jul 12, 2022·0 cites·25 claims
- 3348US2023207406A1Ultra low loss and high-density routing between coresINTEL CORP·Filed 2021·Application pending·0 cites
- 3448US2023100576A1Thick and thin traces in a bridge with a glass coreINTEL CORP·Filed 2021·Application pending·0 cites
- 3546US2023207494A1Single layer and multilayer magnetic inductors between substrate coresXIE JIANYONG·Filed 2021·Application pending·0 cites
- 3645US11545416B2Minimization of insertion loss variation in through-silicon vias (TSVs)INTEL CORP·Filed 2017·Granted Jan 3, 2023·0 cites·27 claims
- 3744US12341129B2Substrateless double-sided embedded multi-die interconnect bridgeINTEL CORP·Filed 2019·Granted Jun 24, 2025·0 cites·20 claims
Join the waitlist — get patent alerts
Get an alert when Jianyong Xie files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →