Inventor · disambiguated record
Jinyong Yuan
Also filed as: YUAN JINYONG
34 granted patents·1 pending application·227 citations·filing 2003–2017
97Inventor score
Top patents by PatentIndex Score
35 records- 0194US9053274B1Register retiming techniqueALTERA CORP·Filed 2014·Granted Jun 9, 2015·14 cites·17 claims
- 0289US7705628B1Programmable logic device having logic elements with dedicated hardware to configure look up tables as registersALTERA CORP·Filed 2006·Granted Apr 27, 2010·13 cites·24 claims
- 0387US7558812B1Structures for LUT-based arithmetic in PLDsALTERA CORP·Filed 2003·Granted Jul 7, 2009·25 cites·12 claims
- 0487US7424689B1Gated clock conversionALTERA CORP·Filed 2006·Granted Sep 9, 2008·16 cites·29 claims
- 0585US7330052B2Area efficient fractureable logic elementsALTERA CORP·Filed 2005·Granted Feb 12, 2008·13 cites·23 claims
- 0683US8806399B1Register retiming techniqueALTERA CORP·Filed 2013·Granted Aug 12, 2014·4 cites·20 claims
- 0783US7386828B1SAT-based technology mapping frameworkALTERA CORP·Filed 2006·Granted Jun 10, 2008·13 cites·20 claims
- 0881US7406668B1Methods for producing mappings of logic suitable for FPGA and structured ASIC implementationsALTERA CORP·Filed 2005·Granted Jul 29, 2008·11 cites·9 claims
- 0980US7246339B2Methods for creating and expanding libraries of structured ASIC logic and other functionsALTERA CORP·Filed 2005·Granted Jul 17, 2007·11 cites·14 claims
- 1079US7360197B1Methods for producing equivalent logic designs for FPGAs and structured ASIC devicesALTERA CORP·Filed 2005·Granted Apr 15, 2008·9 cites·18 claims
- 1178US8245163B1Partial compilation of circuit design with new software version to obtain a complete compiled designYUAN JINYONG·Filed 2008·Granted Aug 14, 2012·17 cites·20 claims
- 1276US7631284B1Graphical user aid for technology migration and associated methodsALTERA CORP·Filed 2005·Granted Dec 8, 2009·8 cites·15 claims
- 1374US7386819B1Methods of verifying functional equivalence between FPGA and structured ASIC logic cellsALTERA CORP·Filed 2005·Granted Jun 10, 2008·6 cites·9 claims
- 1473US9658830B1Structures for LUT-based arithmetic in PLDsALTERA CORP·Filed 2014·Granted May 23, 2017·2 cites·23 claims
- 1573US7890910B1Programmable logic device having logic elements with dedicated hardware to configure look up tables as registersALTERA CORP·Filed 2006·Granted Feb 15, 2011·5 cites·20 claims
- 1670US7992110B1Methods of verifying functional equivalence between FPGA and structured ASIC logic cellsALTERA CORP·Filed 2008·Granted Aug 2, 2011·4 cites·14 claims
- 1769US8601424B1Programmable logic device having logic elements with dedicated hardware to configure look up tables as registersHUTTON MICHAEL D·Filed 2010·Granted Dec 3, 2013·2 cites·20 claims
- 1868US7587688B1User-directed timing-driven synthesisALTERA CORP·Filed 2006·Granted Sep 8, 2009·4 cites·26 claims
- 1968US7373630B1Methods for improved structured ASIC designALTERA CORP·Filed 2005·Granted May 13, 2008·4 cites·20 claims
- 2067US7373631B1Methods of producing application-specific integrated circuit equivalents of programmable logicALTERA CORP·Filed 2004·Granted May 13, 2008·12 cites·17 claims
- 2166US7725871B1SAT-based technology mapping frameworkALTERA CORP·Filed 2008·Granted May 25, 2010·3 cites·9 claims
- 2264US7363596B1Methods for storing and naming static library cells for lookup by logic synthesis and the likeALTERA CORP·Filed 2005·Granted Apr 22, 2008·4 cites·7 claims
- 2363US7308671B1Method and apparatus for performing mapping onto field programmable gate arrays utilizing fracturable logic cellsALTERA CORP·Filed 2004·Granted Dec 11, 2007·8 cites·19 claims
- 2461US7249329B1Technology mapping techniques for incomplete lookup tablesALTERA CORP·Filed 2004·Granted Jul 24, 2007·7 cites·18 claims
- 2559US8006206B1Gated clock conversionALTERA CORP·Filed 2008·Granted Aug 23, 2011·1 cites·20 claims
- 2658US8788550B1Structures for LUT-based arithmetic in PLDsPADALIA KETAN·Filed 2009·Granted Jul 22, 2014·2 cites·20 claims
- 2758US7397726B1Flexible RAM clock enableALTERA CORP·Filed 2006·Granted Jul 8, 2008·3 cites·21 claims
- 2858US2017322775A1Structures for lut-based arithmetic in pldsALTERA CORP·Filed 2017·Application pending·0 cites
- 2957US8191020B1Graphical user aid for technology migration and associated methodsPERRY STEVEN·Filed 2009·Granted May 29, 2012·1 cites·20 claims
- 3053US8443327B2Reassembling scattered logic blocks in integrated circuitsBIN MOHD RAZHA MOHD MAWARDI·Filed 2011·Granted May 14, 2013·2 cites·21 claims
- 3150US9172378B1Programmable logic device having logic elements with dedicated hardware to configure look up tables as registersALTERA CORP·Filed 2013·Granted Oct 27, 2015·0 cites·19 claims
- 3250US8397185B1Graphical user aid for technology migration and associated methodsPERRY STEVEN·Filed 2012·Granted Mar 12, 2013·0 cites·20 claims
- 3350US7415693B1Method and apparatus for reducing synthesis runtimeALTERA CORP·Filed 2004·Granted Aug 19, 2008·1 cites·29 claims
- 3450US7126858B1Apparatus for emulating asynchronous clear in memory structure and method for implementing the sameALTERA CORP·Filed 2005·Granted Oct 24, 2006·2 cites·20 claims
- 3544US8271821B2Flexible RAM clock enableYUAN JINYONG·Filed 2008·Granted Sep 18, 2012·0 cites·16 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →