Inventor · disambiguated record
Jingcheng Zhuang
Also filed as: ZHUANG JINGCHENG
29 granted patents·1 pending application·209 citations·filing 2006–2020
96Inventor score
Top patents by PatentIndex Score
30 records- 0196US10116315B1System-on-a-chip clock phase management using fractional-N PLLsQUALCOMM INC·Filed 2017·Granted Oct 30, 2018·20 cites·17 claims
- 0296US7633322B1Digital loop circuit for programmable logic deviceALTERA CORP·Filed 2007·Granted Dec 15, 2009·48 cites·45 claims
- 0390US11264995B1System and method for maintaining local oscillator (LO) phase continuityQUALCOMM INC·Filed 2020·Granted Mar 1, 2022·4 cites·25 claims
- 0488US9998129B1PLL post divider phase continuityQUALCOMM INC·Filed 2017·Granted Jun 12, 2018·9 cites·20 claims
- 0588US8319579B2Passive filter and AC coupler receiver interfaceZHUANG JINGCHENG·Filed 2010·Granted Nov 27, 2012·13 cites·24 claims
- 0687US8204107B2Bandwidth reduction mechanism for polar modulationZHUANG JINGCHENG·Filed 2008·Granted Jun 19, 2012·14 cites·13 claims
- 0786US7808325B2System and method for frequency pushing/pulling compensationTEXAS INSTRUMENTS INC·Filed 2008·Granted Oct 5, 2010·14 cites·25 claims
- 0885US8461896B2Compensating for wander in AC coupling data interfaceZHUANG JINGCHENG·Filed 2011·Granted Jun 11, 2013·8 cites·21 claims
- 0984US8928365B2Methods and devices for matching transmission line characteristics using stacked metal oxide semiconductor (MOS) transistorsQUALCOMM INC·Filed 2012·Granted Jan 6, 2015·8 cites·21 claims
- 1083US10256796B2Master-slave level shifter array architecture with pre-defined power-up statesQUALCOMM INC·Filed 2017·Granted Apr 9, 2019·9 cites·10 claims
- 1183US9520887B1Glitch free bandwidth-switching scheme for an analog phase-locked loop (PLL)QUALCOMM INC·Filed 2016·Granted Dec 13, 2016·5 cites·30 claims
- 1280US8306174B2Fractional interpolative timing advance and retard control in a transceiverMURPHY THOMAS CASIMIR·Filed 2009·Granted Nov 6, 2012·12 cites·22 claims
- 1379US8497723B2Low-hysteresis high-speed differential samplerZHUANG JINGCHENG·Filed 2011·Granted Jul 30, 2013·5 cites·23 claims
- 1478US9893875B2Phase continuity technique for frequency synthesisQUALCOMM INC·Filed 2016·Granted Feb 13, 2018·3 cites·17 claims
- 1578US8830001B2Low power all digital PLL architectureZHUANG JINGCHENG·Filed 2008·Granted Sep 9, 2014·7 cites·40 claims
- 1677US9864341B1Time-to-digital conversion with latch-based ringQUALCOMM INC·Filed 2016·Granted Jan 9, 2018·2 cites·30 claims
- 1775US7474167B1Capacitance switch circuitry for digitally controlled oscillatorsALTERA CORP·Filed 2006·Granted Jan 6, 2009·6 cites·25 claims
- 1871US8970254B1Systems and methods for frequency detectionQUALCOMM INC·Filed 2014·Granted Mar 3, 2015·3 cites·30 claims
- 1968US10177772B2Fractional-N phase locked loop delta sigma modulator noise reduction using charge pump interpolationQUALCOMM INC·Filed 2016·Granted Jan 8, 2019·2 cites·19 claims
- 2068US8839020B2Dual mode clock/data recovery circuitZHUANG JINGCHENG·Filed 2012·Granted Sep 16, 2014·3 cites·20 claims
- 2168US8014480B1Zero-delay serial communications circuitry for serial interconnectsALTERA CORP·Filed 2007·Granted Sep 6, 2011·6 cites·18 claims
- 2267US8045662B2Binary ripple counter sampling with adjustable delaysTEXAS INSTRUMENTS INC·Filed 2008·Granted Oct 25, 2011·5 cites·6 claims
- 2363US10575279B2Methods and apparatus for a transmit path with frequency hopping phase locked loopQUALCOMM INC·Filed 2016·Granted Feb 25, 2020·1 cites·18 claims
- 2460US9584184B2Unified front-end receiver interface for accommodating incoming signals via AC-coupling or DC-couplingQUALCOMM INC·Filed 2013·Granted Feb 28, 2017·1 cites·28 claims
- 2556US9176511B1Band-gap current repeaterQUALCOMM INC·Filed 2014·Granted Nov 3, 2015·1 cites·20 claims
- 2646US9973182B2Re-timing based clock generation and residual sideband (RSB) enhancement circuitQUALCOMM INC·Filed 2016·Granted May 15, 2018·0 cites·25 claims
- 2745US10534025B2Phase frequency detector linearization using switching supplyQUALCOMM INC·Filed 2017·Granted Jan 14, 2020·0 cites·20 claims
- 2839US7843275B1Frequency synthesizer circuitry employing delay lineALTERA CORP·Filed 2007·Granted Nov 30, 2010·0 cites·14 claims
- 2937US10523272B2Distributed differential interconnectQUALCOMM INC·Filed 2017·Granted Dec 31, 2019·0 cites·30 claims
- 3036US2013216003A1RESETTABLE VOLTAGE CONTROLLED OSCILLATORS (VCOs) FOR CLOCK AND DATA RECOVERY (CDR) CIRCUITS, AND RELATED SYSTEMS AND METHODSZHUANG JINGCHENG·Filed 2012·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →