Inventor · disambiguated record
John W. Bockhaus
Also filed as: BOCKHAUS JOHN W · BOCKHAUS JOHN WILLIAM
16 granted patents·4 pending applications·494 citations·filing 1996–2016
93Inventor score
Files withHEWLETT PACKARD DEVELOPMENT CO6HEWLETT PACKARD CO5BOCKHAUS JOHN W3HEWLETT PACKARD ENTPR DEV LP2LESARTRE GREGG B2
Top patents by PatentIndex Score
20 records- 0188US6374370B1Method and system for flexible control of BIST registers based upon on-chip eventsHEWLETT PACKARD CO·Filed 1998·Granted Apr 16, 2002·158 cites·35 claims
- 0284US5867644ASystem and method for on-chip debug support and performance monitoring in a microprocessorHEWLETT PACKARD CO·Filed 1996·Granted Feb 2, 1999·124 cites·30 claims
- 0381US6003107ACircuitry for providing external access to signals that are internal to an integrated circuit chip packageHEWLETT PACKARD CO·Filed 1996·Granted Dec 14, 1999·98 cites·19 claims
- 0478US10025716B2Mapping processor address ranges to persistent storageHEWLETT PACKARD ENTPR DEV LP·Filed 2016·Granted Jul 17, 2018·2 cites·20 claims
- 0569US7330940B2Method and system for cache utilization by limiting prefetch requestsHEWLETT PACKARD DEVELOPMENT CO·Filed 2005·Granted Feb 12, 2008·6 cites·29 claims
- 0668US5880671AFlexible circuitry and method for detecting signal patterns on a busHEWLETT PACKARD CO·Filed 1996·Granted Mar 9, 1999·55 cites·34 claims
- 0767US10789115B2Transmitter that does not resend a packet despite receipt of a message to resend the packetHEWLETT PACKARD ENTPR DEV LP·Filed 2014·Granted Sep 29, 2020·2 cites·10 claims
- 0865US7328310B2Method and system for cache utilization by limiting number of pending cache line requestsHEWLETT PACKARD DEVELOPMENT CO·Filed 2005·Granted Feb 5, 2008·3 cites·24 claims
- 0965US6944714B2Method and apparatus for saving microprocessor power when sequentially accessing the microprocessor's instruction cacheHEWLETT PACKARD DEVELOPMENT CO·Filed 2002·Granted Sep 13, 2005·14 cites·9 claims
- 1064US8732331B2Managing latencies in a multiprocessor interconnectLESARTRE GREGG B·Filed 2008·Granted May 20, 2014·3 cites·13 claims
- 1162US7721159B2Passing debug informationHEWLETT PACKARD DEVELOPMENT CO·Filed 2005·Granted May 18, 2010·2 cites·30 claims
- 1261US9342452B2Mapping processor address ranges to persistent storageGOSTIN GARY·Filed 2011·Granted May 17, 2016·1 cites·12 claims
- 1361US8225048B2Systems and methods for resource accessLESARTRE GREGG B·Filed 2009·Granted Jul 17, 2012·2 cites·20 claims
- 1459US5644609AApparatus and method for reading and writing remote registers on an integrated circuit chip using a minimum of interconnectsHEWLETT PACKARD CO·Filed 1996·Granted Jul 1, 1997·22 cites·4 claims
- 1557US8000322B2Crossbar switch debuggingHEWLETT PACKARD DEVELOPMENT CO·Filed 2005·Granted Aug 16, 2011·2 cites·14 claims
- 1646US7471623B2Systems and methods for a unified computer system fabricHEWLETT PACKARD DEVELOPMENT CO·Filed 2004·Granted Dec 30, 2008·0 cites·24 claims
- 1742US2004003213A1Method for reducing the latency of a branch target calculation by linking the branch target address cache with the call-return stackFiled 2002·Application pending·0 cites
- 1841US2006179173A1Method and system for cache utilization by prefetching for multiple DMA readsBOCKHAUS JOHN W·Filed 2005·Application pending·0 cites
- 1937US2006179174A1Method and system for preventing cache lines from being flushed until data stored therein is usedBOCKHAUS JOHN W·Filed 2005·Application pending·0 cites
- 2034US2011246833A1Detecting An Unreliable Link In A Computer SystemBOCKHAUS JOHN W·Filed 2008·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →