Inventor · disambiguated record
John H. Crawford
Also filed as: CRAWFORD JOHN · CRAWFORD JOHN H · CRAWFORD JOHN L
53 granted patents·2 pending applications·1,141 citations·filing 1979–2016
99Inventor score
Top patents by PatentIndex Score
55 records- 0197US9934143B2Mapping a physical address differently to different memory devices in a groupINTEL CORP·Filed 2013·Granted Apr 3, 2018·77 cites·19 claims
- 0294US9449671B2Techniques for probabilistic dynamic random access memory row repairINTEL CORP·Filed 2013·Granted Sep 20, 2016·20 cites·23 claims
- 0393US4972338AMemory management for microprocessor systemINTEL CORP·Filed 1988·Granted Nov 20, 1990·137 cites·7 claims
- 0486US9910604B2Refresh parameter-dependent memory refresh managementINTEL CORP·Filed 2016·Granted Mar 6, 2018·4 cites·17 claims
- 0586US8473963B2Synchronizing multiple threads efficientlyKOTTAPALLI SAILESH·Filed 2011·Granted Jun 25, 2013·7 cites·19 claims
- 0683US7984248B2Transaction based shared data operations in a multiprocessor environmentINTEL CORP·Filed 2004·Granted Jul 19, 2011·27 cites·35 claims
- 0783US5321836AVirtual memory management method and apparatus utilizing separate and independent segmentation and paging mechanismINTEL CORP·Filed 1990·Granted Jun 14, 1994·92 cites·6 claims
- 0882US9269436B2Techniques for determining victim row addresses in a volatile memoryINTEL CORP·Filed 2013·Granted Feb 23, 2016·7 cites·25 claims
- 0980US6754689B2Method and apparatus for performing subtraction in redundant form arithmeticINTEL CORP·Filed 2000·Granted Jun 22, 2004·29 cites·30 claims
- 1080US6654909B1Apparatus and method for protecting critical resources against soft errors in high performance microprocessorsINTEL CORP·Filed 2000·Granted Nov 25, 2003·27 cites·19 claims
- 1179US10102886B2Techniques for probabilistic dynamic random access memory row repairINTEL CORP·Filed 2016·Granted Oct 16, 2018·4 cites·23 claims
- 1278US5255378AMethod of transferring burst data in a microprocessorINTEL CORP·Filed 1992·Granted Oct 19, 1993·76 cites·10 claims
- 1376US5530932ACache coherent multiprocessing computer system with reduced power operating featuresINTEL CORP·Filed 1994·Granted Jun 25, 1996·70 cites·8 claims
- 1476US5210845AController for two-way set associative cacheINTEL CORP·Filed 1990·Granted May 11, 1993·75 cites·3 claims
- 1575US8176266B2Transaction based shared data operations in a multiprocessor environmentKOTTAPALLI SAILESH·Filed 2010·Granted May 8, 2012·3 cites·9 claims
- 1675US6163764AEmulation of an instruction set on an instruction set architecture transitionINTEL CORP·Filed 1998·Granted Dec 19, 2000·68 cites·28 claims
- 1771US9857858B2Managing power consumption and performance of computing systemsBODAS DEVADATTA V·Filed 2012·Granted Jan 2, 2018·3 cites·24 claims
- 1871US9824754B2Techniques for determining victim row addresses in a volatile memoryINTEL CORP·Filed 2016·Granted Nov 21, 2017·3 cites·31 claims
- 1971US8458412B2Transaction based shared data operations in a multiprocessor environmentKOTTAPALLI SAILESH·Filed 2011·Granted Jun 4, 2013·2 cites·16 claims
- 2071US6675266B2Circuit and method for protecting 1-hot and 2-hot vector tags in high performance microprocessorsINTEL CORP·Filed 2000·Granted Jan 6, 2004·11 cites·22 claims
- 2170US6542966B1Method and apparatus for managing temporal and non-temporal data in a single cache structureINTEL CORP·Filed 1998·Granted Apr 1, 2003·54 cites·23 claims
- 2270US5809314AMethod of monitoring system bus traffic by a CPU operating with reduced powerINTEL CORP·Filed 1997·Granted Sep 15, 1998·41 cites·5 claims
- 2369US9405595B2Synchronizing multiple threads efficientlyINTEL CORP·Filed 2014·Granted Aug 2, 2016·1 cites·14 claims
- 2468US8887171B2Mechanisms to avoid inefficient core hopping and provide hardware assisted low-power state selectionSONG JUSTIN J·Filed 2009·Granted Nov 11, 2014·4 cites·13 claims
- 2568US6813628B2Method and apparatus for performing equality comparison in redundant form arithmeticINTEL CORP·Filed 2000·Granted Nov 2, 2004·12 cites·12 claims
- 2668US6689989B2Heater for electric blanketFiled 2002·Granted Feb 10, 2004·21 cites·24 claims
- 2767US7315920B2Circuit and method for protecting vector tags in high performance microprocessorsINTEL CORP·Filed 2005·Granted Jan 1, 2008·2 cites·36 claims
- 2866US7669009B2Method and apparatus for run-ahead victim selection to reduce undesirable replacement behavior in inclusive cachesINTEL CORP·Filed 2004·Granted Feb 23, 2010·11 cites·36 claims
- 2966US5948099AApparatus and method for swapping the byte order of a data item to effectuate memory format conversionINTEL CORP·Filed 1991·Granted Sep 7, 1999·46 cites·47 claims
- 3065US5131083AMethod of transferring burst data in a microprocessorINTEL CORP·Filed 1989·Granted Jul 14, 1992·32 cites·18 claims
- 3164US5669003AMethod of monitoring system bus traffic by a CPU operating with reduced powerINTEL CORP·Filed 1994·Granted Sep 16, 1997·34 cites·24 claims
- 3263US9269417B2Memory refresh managementINTEL CORP·Filed 2013·Granted Feb 23, 2016·2 cites·25 claims
- 3363US7937709B2Synchronizing multiple threads efficientlyINTEL CORP·Filed 2004·Granted May 3, 2011·6 cites·21 claims
- 3462US9778720B2PCIE device power state controlKUMAR ANIL K·Filed 2011·Granted Oct 3, 2017·1 cites·12 claims
- 3562US5201043ASystem using both a supervisor level control bit and a user level control bit to enable/disable memory reference alignment checkingINTEL CORP·Filed 1992·Granted Apr 6, 1993·38 cites·10 claims
- 3660US5173872AContent addressable memory for microprocessor systemINTEL CORP·Filed 1987·Granted Dec 22, 1992·27 cites·10 claims
- 3759US7877666B2Tracking health of integrated circuit structuresINTEL CORP·Filed 2006·Granted Jan 25, 2011·1 cites·33 claims
- 3859US6904502B2Circuit and method for protecting 1-hot and 2-hot vector tags in high performance microprocessorsINTEL CORP·Filed 2003·Granted Jun 7, 2005·4 cites·39 claims
- 3959US6826588B2Method and apparatus for a fast comparison in redundant form arithmeticINTEL CORP·Filed 2001·Granted Nov 30, 2004·6 cites·31 claims
- 4059US6775746B2Circuit and method for protecting 1-hot and 2-hot vector tags in high performance microprocessorsINTEL CORP·Filed 2003·Granted Aug 10, 2004·4 cites·27 claims
- 4156US8819684B2Synchronizing multiple threads efficientlyINTEL CORP·Filed 2013·Granted Aug 26, 2014·0 cites·13 claims
- 4255US7607048B2Method and apparatus for protecting TLB's VPN from soft errorsINTEL CORP·Filed 2004·Granted Oct 20, 2009·4 cites·14 claims
- 4354US7010671B2Computer system and method for executing interrupt instructions in two operating modesINTEL CORP·Filed 2002·Granted Mar 7, 2006·2 cites·22 claims
- 4452US6763368B2Method and apparatus for performing single-cycle addition or subtraction and comparison in redundant form arithmeticINTEL CORP·Filed 2000·Granted Jul 13, 2004·2 cites·19 claims
- 4551US6385718B1Computer system and method for executing interrupt instructions in operating modesINTEL CORP·Filed 1997·Granted May 7, 2002·19 cites·14 claims
- 4650US9213390B2Periodic activity alignmentINTEL CORP·Filed 2012·Granted Dec 15, 2015·0 cites·20 claims
- 4750US7383468B2Apparatus and method for protecting critical resources against soft errors in high performance microprocessorINTEL CORP·Filed 2003·Granted Jun 3, 2008·1 cites·19 claims
- 4848US7395304B2Method and apparatus for performing single-cycle addition or subtraction and comparison in redundant form arithmeticINTEL CORP·Filed 2004·Granted Jul 1, 2008·0 cites·13 claims
- 4947US9524009B2Managing the operation of a computing device by determining performance-power statesBODAS DEVADATTA V·Filed 2012·Granted Dec 20, 2016·0 cites·25 claims
- 5047US6839814B2Circuit and method for protecting 1-hot and 2-hot vector tags in high performance microprocessorsINTEL CORP·Filed 2003·Granted Jan 4, 2005·0 cites·36 claims
Showing the top 50 of 55 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →