Inventor · disambiguated record
Joseph A. Czagas
Also filed as: CZAGAS JOSEPH A · CZAGAS JOSEPH ANDRE
10 granted patents·90 citations·filing 1997–2007
90Inventor score
Top patents by PatentIndex Score
10 records- 0190US7285475B2Integrated circuit having a device wafer with a diffused doped backside layerINTERSIL INC·Filed 2005·Granted Oct 23, 2007·12 cites·16 claims
- 0271US6867495B2Integrated circuit having a device wafer with a diffused doped backside layerINTERSIL INC·Filed 2001·Granted Mar 15, 2005·9 cites·32 claims
- 0366US7605052B2Method of forming an integrated circuit having a device wafer with a diffused doped backside layerINTERSIL CORP·Filed 2007·Granted Oct 20, 2009·1 cites·15 claims
- 0465US6946364B2Integrated circuit having a device wafer with a diffused doped backside layerINTERSIL INC·Filed 2004·Granted Sep 20, 2005·6 cites·4 claims
- 0564US6667523B2Highly linear integrated resistive contactINTERSIL INC·Filed 2002·Granted Dec 23, 2003·10 cites·23 claims
- 0658US5976944AIntegrated circuit with thin film resistors and a method for co-patterning thin film resistors with different compositionsHARRIS CORP·Filed 1997·Granted Nov 2, 1999·18 cites·12 claims
- 0756US6362075B1Method for making a diffused back-side layer on a bonded-wafer with a thick bond oxideHARRIS CORP·Filed 1999·Granted Mar 26, 2002·13 cites·26 claims
- 0851US6441447B1Co-patterning thin-film resistors of different compositions with a conductive hard mask and method for sameINTERSIL CORP·Filed 1998·Granted Aug 27, 2002·13 cites·15 claims
- 0949US7110933B2Line modeling toolINTERSIL INC·Filed 2003·Granted Sep 19, 2006·2 cites·47 claims
- 1041US6403472B1Method of forming resistive contacts on intergrated circuits with mobility spoiling ions including high resistive contacts and low resistivity silicide contactsHARRIS CORP·Filed 1999·Granted Jun 11, 2002·6 cites·6 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →