Inventor · disambiguated record
Jonathan James Dement
Also filed as: DEMENT JONATHAN J · DEMENT JONATHAN JAMES
32 granted patents·14 pending applications·319 citations·filing 2003–2009
97Inventor score
Top patents by PatentIndex Score
46 records- 0193US7447602B1System and method for sorting processors based on thermal design pointIBM·Filed 2007·Granted Nov 4, 2008·27 cites·20 claims
- 0292US7350056B2Method and apparatus for issuing instructions from an issue queue in an information handling systemIBM·Filed 2005·Granted Mar 25, 2008·32 cites·17 claims
- 0390US7774616B2Masking a boot sequence by providing a dummy processorIBM·Filed 2006·Granted Aug 10, 2010·23 cites·11 claims
- 0490US7401242B2Dynamic power management in a processor designIBM·Filed 2005·Granted Jul 15, 2008·22 cites·7 claims
- 0589US7159095B2Method of efficiently handling multiple page sizes in an effective to real address translation (ERAT) tableIBM·Filed 2003·Granted Jan 2, 2007·62 cites·4 claims
- 0688US7594104B2System and method for masking a hardware boot sequenceIBM·Filed 2006·Granted Sep 22, 2009·18 cites·3 claims
- 0787US7779273B2Booting a multiprocessor device based on selection of encryption keys to be provided to processorsIBM·Filed 2008·Granted Aug 17, 2010·17 cites·20 claims
- 0887US7313673B2Fine grained multi-thread dispatch block mechanismIBM·Filed 2005·Granted Dec 25, 2007·18 cites·20 claims
- 0985US7490224B2Time-of-life counter design for handling instruction flushes from a queueIBM·Filed 2005·Granted Feb 10, 2009·13 cites·3 claims
- 1082US7681056B2Dynamic power management in a processor designIBM·Filed 2008·Granted Mar 16, 2010·10 cites·7 claims
- 1179US7711903B2Preloading translation buffersIBM·Filed 2007·Granted May 4, 2010·8 cites·18 claims
- 1275US7739573B2Voltage identifier sortingIBM·Filed 2007·Granted Jun 15, 2010·7 cites·20 claims
- 1373US8244979B2System and method for cache-locking mechanism using translation table attributes for replacement class ID determinationBURNS ADAM PATRICK·Filed 2007·Granted Aug 14, 2012·8 cites·17 claims
- 1470US8046574B2Secure boot across a plurality of processorsIBM·Filed 2008·Granted Oct 25, 2011·4 cites·16 claims
- 1570US7913070B2Time-of-life counter for handling instruction flushes from a queueIBM·Filed 2008·Granted Mar 22, 2011·4 cites·2 claims
- 1670US7774617B2Masking a boot sequence by providing a dummy processorIBM·Filed 2008·Granted Aug 10, 2010·4 cites·15 claims
- 1770US7519780B2System and method for reducing store latency in symmetrical multiprocessor systemsIBM·Filed 2006·Granted Apr 14, 2009·5 cites·35 claims
- 1869US8046573B2Masking a hardware boot sequenceIBM·Filed 2008·Granted Oct 25, 2011·3 cites·20 claims
- 1969US7055004B2Pseudo-LRU for a locking cacheIBM·Filed 2003·Granted May 30, 2006·13 cites·24 claims
- 2067US8230495B2Method for security in electronically fused encryption keysBERRY JR ROBERT W·Filed 2009·Granted Jul 24, 2012·3 cites·17 claims
- 2167US7328330B2Queue design supporting dependency checking and issue for SIMD instructions within a general purpose processorIBM·Filed 2005·Granted Feb 5, 2008·3 cites·1 claims
- 2266US8037293B2Selecting a random processor to boot on a multiprocessor systemIBM·Filed 2008·Granted Oct 11, 2011·3 cites·20 claims
- 2366US7917347B2Generating a worst case current waveform for testing of integrated circuit devicesIBM·Filed 2007·Granted Mar 29, 2011·3 cites·20 claims
- 2464US8028151B2Performance of an in-order processor by no longer requiring a uniform completion point across different execution pipelinesIBM·Filed 2008·Granted Sep 27, 2011·2 cites·13 claims
- 2563US7516275B2Pseudo-LRU virtual counter for a locking cacheIBM·Filed 2006·Granted Apr 7, 2009·3 cites·3 claims
- 2663US7370176B2System and method for high frequency stall designIBM·Filed 2005·Granted May 6, 2008·2 cites·6 claims
- 2752US7831808B2Queue design system supporting dependency checking and issue for SIMD instructions within a general purpose processorIBM·Filed 2007·Granted Nov 9, 2010·0 cites·12 claims
- 2852US6967510B2Time-base implementation for correcting accumulative error with chip frequency scalingIBM·Filed 2003·Granted Nov 22, 2005·2 cites·17 claims
- 2952US2008148021A1High Frequency Stall DesignDEMENT JONATHAN JAMES·Filed 2008·Application pending·0 cites
- 3051US7877550B2Bus controller initiated write-through mechanism with hardware automatically generated clean commandIBM·Filed 2008·Granted Jan 25, 2011·0 cites·16 claims
- 3148US7475232B2Performance of an in-order processor by no longer requiring a uniform completion point across different execution pipelinesIBM·Filed 2005·Granted Jan 6, 2009·0 cites·10 claims
- 3247US2005160229A1Method and apparatus for preloading translation buffersIBM·Filed 2004·Application pending·0 cites
- 3345US8099579B2System and method for cache-locking mechanism using segment table attributes for replacement class ID determinationBURNS ADAM PATRICK·Filed 2007·Granted Jan 17, 2012·0 cites·20 claims
- 3445US7472229B2Bus controller initiated write-through mechanismIBM·Filed 2004·Granted Dec 30, 2008·0 cites·18 claims
- 3545US2008034193A1System and Method for Providing a Mediated External Exception Extension for a MicroprocessorDAY MICHAEL N·Filed 2006·Application pending·0 cites
- 3645US2005182912A1Method of effective to real address translation for a multi-threaded microprocessorIBM·Filed 2004·Application pending·0 cites
- 3744US2007118726A1System and method for dynamically selecting storage instruction performance schemeIBM·Filed 2005·Application pending·0 cites
- 3844US2005027960A1Translation look-aside buffer sharing among logical partitionsIBM·Filed 2003·Application pending·0 cites
- 3943US2007198812A1Method and apparatus for issuing instructions from an issue queue including a main issue queue array and an auxiliary issue queue array in an information handling systemIBM·Filed 2005·Application pending·0 cites
- 4043US2006224864A1System and method for handling multi-cycle non-pipelined instruction sequencingDEMENT JONATHAN J·Filed 2005·Application pending·0 cites
- 4143US2007288776A1Method and apparatus for power management in a data processing systemDEMENT JONATHAN JAMES·Filed 2006·Application pending·0 cites
- 4242US2007288738A1System and method for selecting a random processor to boot on a multiprocessor systemDALE JASON N·Filed 2006·Application pending·0 cites
- 4342US2007288761A1System and method for booting a multiprocessor device based on selection of encryption keys to be provided to processorsDALE JASON N·Filed 2006·Application pending·0 cites
- 4442US2007288740A1System and method for secure boot across a plurality of processorsDALE JASON N·Filed 2006·Application pending·0 cites
- 4538US2008092006A1Optimizing a Set of LBIST Patterns to Enhance Delay Fault CoverageDAKWALA NIKHIL·Filed 2006·Application pending·0 cites
- 4637US2007288739A1System and method for masking a boot sequence by running different code on each processorDALE JASON N·Filed 2006·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →