Inventor · disambiguated record
John Edward Derrick
Also filed as: DERRICK JOHN · DERRICK JOHN E · DERRICK JOHN EDWARD
20 granted patents·3 pending applications·655 citations·filing 1995–2024
96Inventor score
Top patents by PatentIndex Score
23 records- 0187US6574727B1Method and apparatus for instruction sampling for performance monitoring and debugIBM·Filed 1999·Granted Jun 3, 2003·136 cites·31 claims
- 0285US5659710ACache coherency method and system employing serially encoded snoop responsesIBM·Filed 1995·Granted Aug 19, 1997·143 cites·19 claims
- 0376US5787486ABus protocol for locked cycle cache hitIBM·Filed 1995·Granted Jul 28, 1998·77 cites·8 claims
- 0472US8065685B2Method, system and apparatus for a transformation engine for use in the processing of structured documentsCERMAK DANIEL M·Filed 2006·Granted Nov 22, 2011·13 cites·5 claims
- 0566US5872980ASemaphore access control buffer and method for accelerated semaphore operationsIBM·Filed 1996·Granted Feb 16, 1999·48 cites·5 claims
- 0665US2025061329A1Content attribution system for artificial intelligence and machine learning systemsDERRICK JOHN E·Filed 2024·Application pending·0 cites
- 0759US5704058ACache bus snoop protocol for optimized multiprocessor computer systemFiled 1995·Granted Dec 30, 1997·36 cites·3 claims
- 0858US6442675B1Compressed string and multiple generation engineIBM·Filed 1999·Granted Aug 27, 2002·31 cites·10 claims
- 0951US6286094B1Method and system for optimizing the fetching of dispatch groups in a superscalar processorIBM·Filed 1999·Granted Sep 4, 2001·23 cites·5 claims
- 1050US6345356B1Method and apparatus for software-based dispatch stall mechanism for scoreboarded IOPsIBM·Filed 1999·Granted Feb 5, 2002·21 cites·18 claims
- 1149US6240507B1Mechanism for multiple register renaming and method thereforIBM·Filed 1998·Granted May 29, 2001·26 cites·19 claims
- 1247US6321380B1Method and apparatus for modifying instruction operations in a processorIBM·Filed 1999·Granted Nov 20, 2001·18 cites·30 claims
- 1344US6289428B1Superscaler processor and method for efficiently recovering from misaligned data addressesIBM·Filed 1999·Granted Sep 11, 2001·16 cites·14 claims
- 1443US5890216AApparatus and method for decreasing the access time to non-cacheable address space in a computer systemIBM·Filed 1997·Granted Mar 30, 1999·15 cites·9 claims
- 1540US6385719B1Method and apparatus for synchronizing parallel pipelines in a superscalar microprocessorIBM·Filed 1999·Granted May 7, 2002·12 cites·14 claims
- 1640US2013067227A1System and Method for Anonymous Digital CommunicationDERRICK JOHN·Filed 2012·Application pending·0 cites
- 1740US2002156977A1Virtual caching of regenerable dataFiled 2001·Application pending·0 cites
- 1839US6336182B1System and method for utilizing a conditional split for aligning internal operation (IOPs) for dispatchIBM·Filed 1999·Granted Jan 1, 2002·11 cites·5 claims
- 1938US6425069B1Optimization of instruction stream execution that includes a VLIW dispatch groupIBM·Filed 1999·Granted Jul 23, 2002·10 cites·6 claims
- 2037US5906659AComputer system buffers for providing concurrency between CPU accesses, local bus accesses, and memory accessesIBM·Filed 1997·Granted May 25, 1999·9 cites·11 claims
- 2132US6304959B1Simplified method to generate BTAGs in a decode unit of a processing systemIBM·Filed 1999·Granted Oct 16, 2001·3 cites·4 claims
- 2231US6430678B1Scoreboard mechanism for serialized string operations utilizing the XERIBM·Filed 1999·Granted Aug 6, 2002·3 cites·10 claims
- 2331US5983025AComputer system buffers for providing concurrency and avoid deadlock conditions between CPU accesses, local bus accesses, and memory accessesIBM·Filed 1995·Granted Nov 9, 1999·4 cites·3 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →