Inventor · disambiguated record
John S. Dodson
Also filed as: DODSON JOHN · DODSON JOHN S · DODSON JOHN STEVE
24 granted patents·130 citations·filing 1999–2021
95Inventor score
Files withIBM24
Top patents by PatentIndex Score
24 records- 0187US9318171B2Dual asynchronous and synchronous memory systemIBM·Filed 2014·Granted Apr 19, 2016·8 cites·12 claims
- 0287US9142272B2Dual asynchronous and synchronous memory systemIBM·Filed 2013·Granted Sep 22, 2015·9 cites·8 claims
- 0380US10297335B2Tracking address ranges for computer memory errorsIBM·Filed 2016·Granted May 21, 2019·4 cites·17 claims
- 0478US10304560B2Performing error correction in computer memoryIBM·Filed 2016·Granted May 28, 2019·2 cites·14 claims
- 0577US10353669B2Managing entries in a mark table of computer memory errorsIBM·Filed 2016·Granted Jul 16, 2019·2 cites·14 claims
- 0677US10338999B2Confirming memory marks indicating an error in computer memoryIBM·Filed 2016·Granted Jul 2, 2019·2 cites·20 claims
- 0777US9136987B2Replay suspension in a memory systemIBM·Filed 2013·Granted Sep 15, 2015·4 cites·20 claims
- 0863US10649511B2Scalable data collection for system managementIBM·Filed 2019·Granted May 12, 2020·0 cites·15 claims
- 0962US6470442B1Processor assigning data to hardware partition based on selectable hash of data addressIBM·Filed 1999·Granted Oct 22, 2002·37 cites·20 claims
- 1061US11017875B2Tracking address ranges for computer memory errorsIBM·Filed 2019·Granted May 25, 2021·0 cites·18 claims
- 1161US10971246B2Performing error correction in computer memoryIBM·Filed 2019·Granted Apr 6, 2021·0 cites·18 claims
- 1255US10317964B2Scalable data collection for system managementIBM·Filed 2016·Granted Jun 11, 2019·0 cites·20 claims
- 1354US12118236B2Dynamically allocating memory controller resources for extended prefetchingIBM·Filed 2021·Granted Oct 15, 2024·0 cites·19 claims
- 1454US9250666B2Scalable data collection for system managementIBM·Filed 2012·Granted Feb 2, 2016·0 cites·19 claims
- 1540US6823471B1Method for providing high availability within a data processing system via a reconfigurable hashed storage subsystemIBM·Filed 1999·Granted Nov 23, 2004·12 cites·15 claims
- 1640US6658556B1Hashing a target address for a memory access instruction in order to determine prior to execution which particular load/store unit processes the instructionIBM·Filed 1999·Granted Dec 2, 2003·11 cites·13 claims
- 1738US6516404B1Data processing system having hashed architected processor facilitiesIBM·Filed 1999·Granted Feb 4, 2003·10 cites·20 claims
- 1837US6446165B1Address dependent caching behavior within a data processing system having HSA (hashed storage architecture)IBM·Filed 1999·Granted Sep 3, 2002·9 cites·23 claims
- 1935US6249911B1Optimizing compiler for generating store instructions having memory hierarchy control bitsIBM·Filed 1999·Granted Jun 19, 2001·6 cites·7 claims
- 2035US6249843B1Store instruction having horizontal memory hierarchy control bitsIBM·Filed 1999·Granted Jun 19, 2001·6 cites·20 claims
- 2132US6598118B1Data processing system with HSA (hashed storage architecture)IBM·Filed 1999·Granted Jul 22, 2003·3 cites·21 claims
- 2232US6253286B1Apparatus for adjusting a store instruction having memory hierarchy control bitsIBM·Filed 1999·Granted Jun 26, 2001·4 cites·12 claims
- 2330US6449691B1Asymmetrical cache properties within a hashed storage subsystemIBM·Filed 1999·Granted Sep 10, 2002·1 cites·21 claims
- 2430US6230242B1Store instruction having vertical memory hierarchy control bitsIBM·Filed 1999·Granted May 8, 2001·0 cites·15 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →