Inventor · disambiguated record
John H. Edmondson
Also filed as: EDMONDSON JOHN · EDMONDSON JOHN H
61 granted patents·6 pending applications·1,997 citations·filing 1992–2025
99Inventor score
Top patents by PatentIndex Score
67 records- 0199US7805587B1Memory addressing controlled by PTE fieldsNVIDIA CORP·Filed 2006·Granted Sep 28, 2010·440 cites·20 claims
- 0298US8072463B1Graphics system with virtual memory pages and non-power of two number of memory elementsVAN DYKE JAMES M·Filed 2006·Granted Dec 6, 2011·108 cites·20 claims
- 0398US7872657B1Memory addressing scheme using partition stridesNVIDIA CORP·Filed 2006·Granted Jan 18, 2011·42 cites·20 claims
- 0498US7620793B1Mapping memory partitions to virtual memory pagesNVIDIA CORP·Filed 2006·Granted Nov 17, 2009·93 cites·18 claims
- 0596US8365015B1Memory-based error recoveryNVIDIA CORP·Filed 2010·Granted Jan 29, 2013·39 cites·19 claims
- 0695US8244984B1System and method for cleaning dirty data in an intermediate cache using a data class dependent eviction policyGLASCO DAVID B·Filed 2008·Granted Aug 14, 2012·53 cites·21 claims
- 0795US7830392B1Connecting multiple pixel shaders to a frame buffer without a crossbarNVIDIA CORP·Filed 2006·Granted Nov 9, 2010·16 cites·10 claims
- 0893US8928681B1Coalescing to avoid read-modify-write during compressed data operationsEDMONDSON JOHN H·Filed 2009·Granted Jan 6, 2015·13 cites·15 claims
- 0991US12020035B2Programmatically controlled data multicasting across multiple compute enginesNVIDIA CORP·Filed 2022·Granted Jun 25, 2024·3 cites·21 claims
- 1091US5347648AEnsuring write ordering under writeback cache error conditionsDIGITAL EQUIPMENT CORP·Filed 1992·Granted Sep 13, 1994·188 cites·20 claims
- 1190US8234478B1Using a data cache array as a DRAM load/store bufferROBERTS JAMES·Filed 2008·Granted Jul 31, 2012·23 cites·18 claims
- 1290US7868901B1Method and system for reducing memory bandwidth requirements in an anti-aliasing operationNVIDIA CORP·Filed 2006·Granted Jan 11, 2011·9 cites·20 claims
- 1389US8321618B1Managing conflicts on shared L2 busKEIL SHANE·Filed 2009·Granted Nov 27, 2012·23 cites·25 claims
- 1489US8131931B1Configurable cache occupancy policyROBERTS JAMES·Filed 2008·Granted Mar 6, 2012·20 cites·24 claims
- 1589US7808507B1Compression tag state interlockNVIDIA CORP·Filed 2006·Granted Oct 5, 2010·8 cites·18 claims
- 1689US5317720AProcessor system with writeback cache using writeback and non writeback transactions stored in separate queuesDIGITAL EQUIPMENT CORP·Filed 1993·Granted May 31, 1994·168 cites·30 claims
- 1788US9058792B1Coalescing to avoid read-modify-write during compressed data operationsEDMONDSON JOHN H·Filed 2006·Granted Jun 16, 2015·8 cites·14 claims
- 1888US8341358B1System and method for cleaning dirty data in a cache via frame buffer logicEDMONDSON JOHN H·Filed 2009·Granted Dec 25, 2012·18 cites·20 claims
- 1988US8060700B1System, method and frame buffer logic for evicting dirty data from a cache using counters and data typesGLASCO DAVID B·Filed 2008·Granted Nov 15, 2011·18 cites·20 claims
- 2087US8195858B1Managing conflicts on shared L2 busKEIL SHANE·Filed 2009·Granted Jun 5, 2012·18 cites·26 claims
- 2187US5471591ACombined write-operand queue and read-after-write dependency scoreboardDIGITAL EQUIPMENT CORP·Filed 1992·Granted Nov 28, 1995·146 cites·18 claims
- 2286US8700865B1Compressed data access system and methodVAN DYKE JAMES M·Filed 2006·Granted Apr 15, 2014·15 cites·19 claims
- 2386US8441495B1Compression tag state interlockVAN DYKE JAMES M·Filed 2009·Granted May 14, 2013·6 cites·12 claims
- 2482US8139073B1Early compression tag lookup for memory accessesVAN DYKE JAMES M·Filed 2006·Granted Mar 20, 2012·13 cites·20 claims
- 2581US8949541B2Techniques for evicting dirty data from a cache using a notification sorter and count thresholdsGLASCO DAVID B·Filed 2011·Granted Feb 3, 2015·6 cites·20 claims
- 2680US10459861B2Unified cache for diverse memory trafficNVIDIA CORP·Filed 2017·Granted Oct 29, 2019·2 cites·21 claims
- 2780US6807186B2Architectures for a single-stage grooming switchLSI LOGIC CORP·Filed 2002·Granted Oct 19, 2004·18 cites·61 claims
- 2880US6108770AMethod and apparatus for predicting memory dependence using store setsDIGITAL EQUIPMENT CORP·Filed 1998·Granted Aug 22, 2000·93 cites·39 claims
- 2979US7685371B1Hierarchical flush barrier mechanism with deadlock avoidanceNVIDIA CORP·Filed 2006·Granted Mar 23, 2010·9 cites·11 claims
- 3079US7664905B2Page stream sorter for poor locality access patternsNVIDIA CORP·Filed 2006·Granted Feb 16, 2010·11 cites·22 claims
- 3178US10095548B2Mechanism for waking common resource requests within a resource management subsystemFETTERMAN MICHAEL·Filed 2012·Granted Oct 9, 2018·5 cites·21 claims
- 3277US8464001B1Cache and associated method with frame buffer managed dirty data pull and high-priority clean mechanismEDMONDSON JOHN H·Filed 2008·Granted Jun 11, 2013·8 cites·13 claims
- 3377US7111155B1Digital signal processor computation core with input operand selection from operand bus for dual operationsANALOG DEVICES INC·Filed 2000·Granted Sep 19, 2006·27 cites·9 claims
- 3476US8656093B1Supporting late DRAM bank hitsEDMONDSON JOHN H·Filed 2008·Granted Feb 18, 2014·7 cites·18 claims
- 3575US7257183B2Digital clock recovery circuitRAMBUS INC·Filed 2002·Granted Aug 14, 2007·17 cites·26 claims
- 3675US5542058APipelined computer with operand context queue to simplify context-dependent execution flowDIGITAL EQUIPMENT CORP·Filed 1994·Granted Jul 30, 1996·66 cites·20 claims
- 3772US2025272107A1Cooperative Group ArraysNVIDIA CORP·Filed 2025·Application pending·0 cites
- 3871US8307165B1Sorting requests to the DRAM for high page localityKEIL SHANE·Filed 2009·Granted Nov 6, 2012·5 cites·24 claims
- 3971US6820189B1Computation core executing multiple operation DSP instructions and micro-controller instructions of shorter length without performing switch operationANALOG DEVICES INC·Filed 2000·Granted Nov 16, 2004·17 cites·8 claims
- 4070US7275123B2Method and apparatus for providing peer-to-peer data transfer within a computing environmentNVIDIA CORP·Filed 2004·Granted Sep 25, 2007·13 cites·20 claims
- 4169US8375163B1Supporting late DRAM bank hitsNVIDIA CORP·Filed 2008·Granted Feb 12, 2013·4 cites·27 claims
- 4269US5278783AFast area-efficient multi-bit binary adder with low fan-out signalsDIGITAL EQUIPMENT CORP·Filed 1992·Granted Jan 11, 1994·52 cites·30 claims
- 4367US5680544AMethod for testing an on-chip cache for repairDIGITAL EQUIPMENT CORP·Filed 1995·Granted Oct 21, 1997·26 cites·21 claims
- 4466US12333311B2Cooperative group arraysNVIDIA CORP·Filed 2022·Granted Jun 17, 2025·0 cites·20 claims
- 4566US12248788B2Distributed shared memoryNVIDIA CORP·Filed 2022·Granted Mar 11, 2025·0 cites·24 claims
- 4666US11347668B2Unified cache for diverse memory trafficNVIDIA CORP·Filed 2020·Granted May 31, 2022·0 cites·20 claims
- 4766US8539130B2Virtual channels for effective packet transferGLASCO DAVID B·Filed 2010·Granted Sep 17, 2013·2 cites·22 claims
- 4866US6859872B1Digital signal processor computation core with pipeline having memory access stages and multiply accumulate stages positioned for efficient operationANALOG DEVICES INC·Filed 2000·Granted Feb 22, 2005·12 cites·10 claims
- 4965US2025173152A1Distributed Shared MemoryNVIDIA CORP·Filed 2025·Application pending·0 cites
- 5063US9245601B2High-density latch arraysNVIDIA CORP·Filed 2014·Granted Jan 26, 2016·1 cites·18 claims
Showing the top 50 of 67 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →