Inventor · disambiguated record
Joseph J. Jasniewski
Also filed as: JASNIEWSKI JOSEPH J
3 granted patents·2 pending applications·13 citations·filing 2015–2015
62Inventor score
Top patents by PatentIndex Score
5 records- 0191US10260961B2Integrated circuit packages with temperature sensor tracesINTEL CORP·Filed 2015·Granted Apr 16, 2019·8 cites·25 claims
- 0284US10178763B2Warpage mitigation in printed circuit board assembliesINTEL CORP·Filed 2015·Granted Jan 8, 2019·5 cites·25 claims
- 0336US9991223B2Semiconductor package alignment frame for local reflowINTEL CORP·Filed 2015·Granted Jun 5, 2018·0 cites·14 claims
- 0432US2017178994A1Integrated circuit package support structuresINTEL CORP·Filed 2015·Application pending·0 cites
- 0527US2017179066A1Bulk solder removal on processor packagingAOKI RUSSELL S·Filed 2015·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →