Inventor · disambiguated record
Jocelyn Francois Orion Jaubert
Also filed as: JAUBERT JOCELYN FRANCOIS ORION · JAUBERT JOCELYN FRANÇOIS ORION
13 granted patents·16 citations·filing 2006–2021
85Inventor score
Technology areasG06F
Files withADVANCED RISC MACH LTD10CHAUSSADE NICOLAS1JAUBERT JOCELYN FRANCOIS ORION1TEYSSIER MELANIE EMANUELLE LUCIE1
Top patents by PatentIndex Score
13 records- 0173US10540299B2Resetting operating state holding elementADVANCED RISC MACH LTD·Filed 2017·Granted Jan 21, 2020·2 cites·12 claims
- 0273US10445500B2Reset attack detectionADVANCED RISC MACH LTD·Filed 2017·Granted Oct 15, 2019·2 cites·9 claims
- 0372US9361112B2Return address predictionADVANCED RISC MACH LTD·Filed 2013·Granted Jun 7, 2016·4 cites·19 claims
- 0468US10572262B2Register mapping of register specifiers to registers depending on a key value used for mapping at least two of the register specifiersADVANCED RISC MACH LTD·Filed 2017·Granted Feb 25, 2020·1 cites·19 claims
- 0565US8578139B2Checkpointing long latency instruction as fake branch in branch prediction mechanismCHAUSSADE NICOLAS·Filed 2010·Granted Nov 5, 2013·2 cites·10 claims
- 0664US7650483B2Execution of instructions within a data processing apparatus having a plurality of processing unitsADVANCED RISC MACH LTD·Filed 2006·Granted Jan 19, 2010·3 cites·18 claims
- 0761US8352794B2Control of clock gatingADVANCED RISC MACH LTD·Filed 2009·Granted Jan 8, 2013·2 cites·21 claims
- 0851US9513925B2Marking long latency instruction as branch in pending instruction table and handle as mis-predicted branch upon interrupting event to return to checkpointed stateADVANCED RISC MACH LTD·Filed 2013·Granted Dec 6, 2016·0 cites·12 claims
- 0944US10902113B2Data processingADVANCED RISC MACH LTD·Filed 2017·Granted Jan 26, 2021·0 cites·12 claims
- 1043US9323536B2Identification of missing call and return instructions for management of a return address stackADVANCED RISC MACH LTD·Filed 2013·Granted Apr 26, 2016·0 cites·19 claims
- 1139US11531547B2Data processingADVANCED RISC MACH LTD·Filed 2021·Granted Dec 20, 2022·0 cites·13 claims
- 1233US8458532B2Error handling mechanism for a tag memory within coherency control circuitryJAUBERT JOCELYN FRANCOIS ORION·Filed 2010·Granted Jun 4, 2013·0 cites·16 claims
- 1332US9189432B2Apparatus and method for predicting target storage unitTEYSSIER MELANIE EMANUELLE LUCIE·Filed 2010·Granted Nov 17, 2015·0 cites·19 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →