Inventor · disambiguated record
Joel Landry
Also filed as: LANDRY JOEL · LANDRY JOEL D
11 granted patents·263 citations·filing 1996–2019
89Inventor score
Top patents by PatentIndex Score
11 records- 0196US5744980AFlexible, high-performance static RAM architecture for field-programmable gate arraysACTEL CORP·Filed 1996·Granted Apr 28, 1998·190 cites·14 claims
- 0291US7616508B1Flash-based FPGA with secure reprogrammingACTEL CORP·Filed 2006·Granted Nov 10, 2009·24 cites·10 claims
- 0390US7701246B1Programmable delay line compensated for process, voltage, and temperatureACTEL CORP·Filed 2008·Granted Apr 20, 2010·22 cites·11 claims
- 0484US7683660B1Programmable logic device with a microcontroller-based control systemACTEL CORP·Filed 2008·Granted Mar 23, 2010·12 cites·8 claims
- 0583US7885122B2Flash-based FPGA with secure reprogrammingACTEL CORP·Filed 2009·Granted Feb 8, 2011·12 cites·8 claims
- 0671US10936286B2FPGA logic cell with improved support for countersMICROSEMI SOC CORP·Filed 2019·Granted Mar 2, 2021·2 cites·5 claims
- 0754US10020811B2FPGA RAM blocks optimized for use as register filesMICROSEMI SOC CORP·Filed 2017·Granted Jul 10, 2018·0 cites·16 claims
- 0849US9780792B2FPGA RAM blocks optimized for use as register filesMICROSEMI SOC CORP·Filed 2013·Granted Oct 3, 2017·0 cites·7 claims
- 0949US7924051B2Programmable logic device with a microcontroller-based control systemACTEL CORP·Filed 2010·Granted Apr 12, 2011·0 cites·8 claims
- 1046US8067959B2Programmable delay line compensated for process, voltage, and temperaturePLANTS WILLIAM C·Filed 2010·Granted Nov 29, 2011·1 cites·13 claims
- 1145US8446170B2FPGA RAM blocks optimized for use as register filesLANDRY JOEL·Filed 2012·Granted May 21, 2013·0 cites·5 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →