Inventor · disambiguated record
John S. Lechaton
Also filed as: LECHATON JOHN S
17 granted patents·1 pending application·550 citations·filing 1976–2016
96Inventor score
Top patents by PatentIndex Score
18 records- 0193US4960726ABiCMOS processIBM·Filed 1989·Granted Oct 2, 1990·78 cites·10 claims
- 0290US4131533ARF sputtering apparatus having floating anode shieldIBM·Filed 1977·Granted Dec 26, 1978·64 cites·16 claims
- 0385US4726879ARIE process for etching silicon isolation trenches and polycides with vertical surfacesIBM·Filed 1986·Granted Feb 23, 1988·79 cites·22 claims
- 0484US7225915B2Mountable cleaning apparatus for commercial conveyorsKELLY CAROL LYNN·Filed 2005·Granted Jun 5, 2007·23 cites·20 claims
- 0581US4502913ATotal dielectric isolation for integrated circuitsIBM·Filed 1982·Granted Mar 5, 1985·50 cites·22 claims
- 0676US8360006B2Cat litter box liner with an absorbent scratch resistant padLECHATON JOHN S·Filed 2011·Granted Jan 29, 2013·10 cites·8 claims
- 0776US4090006AStructure for making coplanar layers of thin filmsIBM·Filed 1977·Granted May 16, 1978·30 cites·5 claims
- 0870US4389281AMethod of planarizing silicon dioxide in semiconductor devicesIBM·Filed 1980·Granted Jun 21, 1983·32 cites·6 claims
- 0969US4435898AMethod for making a base etched transistor integrated circuitIBM·Filed 1982·Granted Mar 13, 1984·31 cites·12 claims
- 1066US4029562AForming feedthrough connections for multi-level interconnections metallurgy systemsIBM·Filed 1976·Granted Jun 14, 1977·24 cites·6 claims
- 1163US4661832ATotal dielectric isolation for integrated circuitsIBM·Filed 1986·Granted Apr 28, 1987·29 cites·12 claims
- 1260US4035276AMaking coplanar layers of thin filmsIBM·Filed 1976·Granted Jul 12, 1977·15 cites·21 claims
- 1357US5086016AMethod of making semiconductor device contact including transition metal-compound dopant sourceIBM·Filed 1990·Granted Feb 4, 1992·27 cites·5 claims
- 1455US4752817AHigh performance integrated circuit having modified extrinsic baseIBM·Filed 1986·Granted Jun 21, 1988·16 cites·10 claims
- 1555US4573256AMethod for making a high performance transistor integrated circuitIBM·Filed 1983·Granted Mar 4, 1986·13 cites·12 claims
- 1655US4535531AMethod and resulting structure for selective multiple base width transistor structuresIBM·Filed 1982·Granted Aug 20, 1985·19 cites·15 claims
- 1739US5279987AFabricating planar complementary patterned subcollectors with silicon epitaxial layerIBM·Filed 1991·Granted Jan 18, 1994·10 cites·8 claims
- 1834US2018136347A1Solid State Structure and Method for Detecting NeutrinosLECHATON JOHN S·Filed 2016·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →