Inventor · disambiguated record
John S. Liptay
Also filed as: LIPTAY JOHN S · LIPTAY JOHN STEPHEN
30 granted patents·1 pending application·1,219 citations·filing 1978–2004
98Inventor score
Technology areasG06F
Files withIBM31
Top patents by PatentIndex Score
31 records- 0194US4200927AMulti-instruction stream branch processing mechanismIBM·Filed 1978·Granted Apr 29, 1980·306 cites·8 claims
- 0293US4901233AComputer system with logic for writing instruction identifying data into array control lists for precise post-branch recoveriesIBM·Filed 1987·Granted Feb 13, 1990·162 cites·2 claims
- 0389US5134561AComputer system with logic for writing instruction identifying data into array control lists for precise post-branch recoveriesIBM·Filed 1989·Granted Jul 28, 1992·105 cites·13 claims
- 0485US5504859AData processor with enhanced error recoveryIBM·Filed 1993·Granted Apr 2, 1996·118 cites·16 claims
- 0579US4189772AOperand alignment controls for VFL instructionsIBM·Filed 1978·Granted Feb 19, 1980·40 cites·22 claims
- 0679US4189768AOperand fetch control improvementIBM·Filed 1978·Granted Feb 19, 1980·41 cites·3 claims
- 0778US6865645B1Program store compare handling between instruction and operand cachesIBM·Filed 2000·Granted Mar 8, 2005·27 cites·25 claims
- 0875US4189770ACache bypass control for operand fetchesIBM·Filed 1978·Granted Feb 19, 1980·35 cites·6 claims
- 0971US5495590ACheckpoint synchronization with instruction overlap enabledIBM·Filed 1995·Granted Feb 27, 1996·55 cites·6 claims
- 1065US6671794B1Address generation interlock detectionIBM·Filed 2000·Granted Dec 30, 2003·11 cites·25 claims
- 1161US5257354ASystem for monitoring and undoing execution of instructions beyond a serialization point upon occurrence of in-correct resultsIBM·Filed 1991·Granted Oct 26, 1993·38 cites·13 claims
- 1261US4287561AAddress formulation interlock mechanismIBM·Filed 1979·Granted Sep 1, 1981·22 cites·4 claims
- 1356US5790844AMillicode load and test access instruction that blocks interrupts in response to access exceptionsIBM·Filed 1997·Granted Aug 4, 1998·23 cites·1 claims
- 1455US6745313B2Absolute address bits kept in branch history tableIBM·Filed 2002·Granted Jun 1, 2004·4 cites·18 claims
- 1555US6662296B1Method and system for testing millicode branch pointsIBM·Filed 2000·Granted Dec 9, 2003·4 cites·33 claims
- 1653US5748951ASpecialized millicode instructions which reduce cycle time and number of instructions necessary to perform complex operationsIBM·Filed 1997·Granted May 5, 1998·21 cites·1 claims
- 1752US5694587ASpecialized millicode instructions for test PSW validity, load with access test, and character translation assistIBM·Filed 1995·Granted Dec 2, 1997·20 cites·1 claims
- 1851US5495587AMethod for processing checkpoint instructions to allow concurrent execution of overlapping instructionsIBM·Filed 1994·Granted Feb 27, 1996·20 cites·6 claims
- 1950US6751708B2Method for ensuring that a line is present in an instruction cacheIBM·Filed 2002·Granted Jun 15, 2004·1 cites·21 claims
- 2049US5903479AMethod and system for executing denormalized numbersIBM·Filed 1997·Granted May 11, 1999·22 cites·14 claims
- 2147US6125444AMillimode capable computer system providing global branch history table disables and separate millicode disables which enable millicode disable to be turned off for some sections of code execution but not disabled for allIBM·Filed 1998·Granted Sep 26, 2000·18 cites·14 claims
- 2246US6108776AGlobally or selectively disabling branch history table operations during sensitive portion of millicode routine in millimode supporting computerIBM·Filed 1998·Granted Aug 22, 2000·18 cites·9 claims
- 2346US2005257035A1Linked instruction buffering of basic blocks for asynchronous predicted taken branchesIBM·Filed 2004·Application pending·0 cites
- 2445US5713035ALinking program access register number with millicode operand accessIBM·Filed 1995·Granted Jan 27, 1998·18 cites·8 claims
- 2544US6035392AComputer with optimizing hardware for conditional hedge fetching into cache storageIBM·Filed 1998·Granted Mar 7, 2000·17 cites·7 claims
- 2642US6138223AAbsolute address history table index generation for predicting instruction and operand cache accessesIBM·Filed 1998·Granted Oct 24, 2000·14 cites·8 claims
- 2742US5649155ACache memory accessed by continuation requestsIBM·Filed 1995·Granted Jul 15, 1997·19 cites·18 claims
- 2841US6085313AComputer processor system for executing RXE format floating point instructionsIBM·Filed 1998·Granted Jul 4, 2000·13 cites·3 claims
- 2940US6105126AAddress bit decoding for same adder circuitry for RXE instruction format with same XBD location as RX format and dis-jointed extended operation codeIBM·Filed 1998·Granted Aug 15, 2000·12 cites·3 claims
- 3036US5625808ARead only store as part of cache store for storing frequently used millicode instructionsIBM·Filed 1995·Granted Apr 29, 1997·11 cites·6 claims
- 3132US6026488AMethod for conditional hedge fetching into cache storageIBM·Filed 1998·Granted Feb 15, 2000·4 cites·8 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →