Inventor · disambiguated record
Jonathan Lotz
Also filed as: LOTZ JONATHAN · LOTZ JONATHAN P
18 granted patents·4 pending applications·343 citations·filing 1996–2011
94Inventor score
Top patents by PatentIndex Score
22 records- 0186US6937527B1High reliability triple redundant latch with voting logic on each storage nodeHEWLETT PACKARD DEVELOPMENT CO·Filed 2004·Granted Aug 30, 2005·29 cites·27 claims
- 0284US5867644ASystem and method for on-chip debug support and performance monitoring in a microprocessorHEWLETT PACKARD CO·Filed 1996·Granted Feb 2, 1999·124 cites·30 claims
- 0373US7179690B2High reliability triple redundant latch with voting logic on each storage nodeHEWLETT PACKARD DEVELOPMENT CO·Filed 2005·Granted Feb 20, 2007·7 cites·7 claims
- 0468US6930527B1Triple redundant latch design with storage node recoveryHEWLETT PACKARD DEVELOPMENT CO·Filed 2004·Granted Aug 16, 2005·14 cites·22 claims
- 0567US5796997AFast nullify system and method for transforming a nullify function into a select functionHEWLETT PACKARD CO·Filed 1996·Granted Aug 18, 1998·53 cites·12 claims
- 0660US7215581B2Triple redundant latch design with low delay timeHEWLETT PACKARD DEVELOPMENT CO·Filed 2004·Granted May 8, 2007·9 cites·30 claims
- 0757US7095262B2High reliability triple redundant latch with integrated testabilityHEWLETT PACKARD DEVELOPMENT CO·Filed 2004·Granted Aug 22, 2006·9 cites·38 claims
- 0855US5748934AOperand dependency tracking system and method for a processor that executes instructions out of order and that permits multiple precision data wordsHEWLETT PACKARD CO·Filed 1996·Granted May 5, 1998·33 cites·8 claims
- 0950US5784587AMethod and system for recovering from cache missesHEWLETT PACKARD CO·Filed 1996·Granted Jul 21, 1998·25 cites·8 claims
- 1045US5901061AMethod of checking for races in a digital designHEWLETT PACKARD CO·Filed 1996·Granted May 4, 1999·18 cites·19 claims
- 1144US6492838B2System and method for improving performance of dynamic circuitsHEWLETT PACKARD CO·Filed 2001·Granted Dec 10, 2002·3 cites·22 claims
- 1242US6380022B1Method for creating a useful biopolar junction transistor from a parasitic bipolar junction transistor on a MOSFETHEWLETT PACKARD CO·Filed 2000·Granted Apr 30, 2002·1 cites·12 claims
- 1342US2007261059A1Array-based memory abstractionORTH JOSEPH F·Filed 2006·Application pending·0 cites
- 1441US7054203B2High reliability memory element with improved delay timeHEWLETT PACKARD DEVELOPMENT CO·Filed 2004·Granted May 30, 2006·2 cites·28 claims
- 1541US2003084249A1Preemptive eviction of stale entries is a computer cache by use of age-bitsFiled 2001·Application pending·0 cites
- 1641US2003084253A1Identification of stale entries in a computer cacheFiled 2001·Application pending·0 cites
- 1738US6624482B2Method for creating a useful bipolar junction transistor from a parasitic bipolar junction transistor on a MOSFETHEWLETT PACKARD DEVELOPMENT CO·Filed 2002·Granted Sep 23, 2003·0 cites·3 claims
- 1838US2012292777A1Backside Power Delivery Using Die StackingLOTZ JONATHAN P·Filed 2011·Application pending·0 cites
- 1937US6584600B2Hierarchical metal one usage tool for child level leaf cellHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Jun 24, 2003·0 cites·20 claims
- 2035US7027333B2High reliability triple redundant memory element with integrated testability and voting structures on each latchHEWLETT PACKARD DEVELOPMENT CO·Filed 2004·Granted Apr 11, 2006·2 cites·19 claims
- 2134US5805851ASystem for determining data dependencies among intra-bundle instructions queued and prior instructions in the queueHEWLETT PACKARD CO·Filed 1996·Granted Sep 8, 1998·7 cites·9 claims
- 2233US5838944ASystem for storing processor register data after a mispredicted branchHEWLETT PACKARD CO·Filed 1996·Granted Nov 17, 1998·7 cites·12 claims
Join the waitlist — get patent alerts
Get an alert when Jonathan Lotz files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →