Inventor · disambiguated record
John V. Lovelace
Also filed as: LOVELACE JOHN V · LOVELACE JOHN VAN
27 granted patents·4 pending applications·635 citations·filing 1998–2021
97Inventor score
Top patents by PatentIndex Score
31 records- 0194US9025399B1Method for training a control signal based on a strobe signal in a memory moduleINTEL CORP·Filed 2013·Granted May 5, 2015·36 cites·25 claims
- 0290US6263431B1Operating system bootstrap security mechanismINTLE CORP·Filed 1998·Granted Jul 17, 2001·254 cites·10 claims
- 0389US9330734B2Method and apparatus for dynamically adjusting voltage reference to optimize an I/O systemINTEL CORP·Filed 2013·Granted May 3, 2016·9 cites·13 claims
- 0488US7305668B2Secure method to perform computer system firmware updatesINTEL CORP·Filed 2002·Granted Dec 4, 2007·80 cites·35 claims
- 0587US9627029B2Method for training a control signal based on a strobe signal in a memory moduleINTEL CORP·Filed 2015·Granted Apr 18, 2017·9 cites·9 claims
- 0687US8819474B2Active training of memory command timingSCHOENBORN THEODORE Z·Filed 2009·Granted Aug 26, 2014·21 cites·22 claims
- 0787US7213152B1Modular bios update mechanismINTEL CORP·Filed 2000·Granted May 1, 2007·57 cites·23 claims
- 0886US10891243B2Memory bus MR register programming processINTEL CORP·Filed 2019·Granted Jan 12, 2021·4 cites·21 claims
- 0986US10148416B2Signal phase optimization in memory interface trainingINTEL CORP·Filed 2016·Granted Dec 4, 2018·8 cites·15 claims
- 1086US8582374B2Method and apparatus for dynamically adjusting voltage reference to optimize an I/O systemMOZAK CHRISTOPHER·Filed 2009·Granted Nov 12, 2013·18 cites·19 claims
- 1184US10347319B2Method and apparatus for dynamically adjusting voltage reference to optimize an I/O systemINTEL CORP·Filed 2016·Granted Jul 9, 2019·5 cites·19 claims
- 1283US8331176B2Method and system for evaluating effects of signal phase difference on a memory systemMOZAK CHRISTOPHER P·Filed 2009·Granted Dec 11, 2012·16 cites·19 claims
- 1380US7036007B2Firmware architecture supporting safe updates and multiple processor typesINTEL CORP·Filed 2002·Granted Apr 25, 2006·38 cites·28 claims
- 1479US9373365B2Method and apparatus for dynamically adjusting voltage reference to optimize an I/O systemINTEL CORP·Filed 2014·Granted Jun 21, 2016·4 cites·17 claims
- 1578US10380043B2Memory bus MR register programming processINTEL CORP·Filed 2017·Granted Aug 13, 2019·2 cites·22 claims
- 1677US10621121B2Measurement and optimization of command signal timing marginsINTEL CORP·Filed 2017·Granted Apr 14, 2020·3 cites·20 claims
- 1777US7949850B2Methods and appratus for demand-based memory mirroringINTEL CORP·Filed 2007·Granted May 24, 2011·9 cites·21 claims
- 1876US9852021B2Method and apparatus for encoding registers in a memory moduleINTEL CORP·Filed 2015·Granted Dec 26, 2017·3 cites·18 claims
- 1974US9318182B2Apparatus, method and system to determine memory access command timing based on error detectionLOVELACE JOHN V·Filed 2013·Granted Apr 19, 2016·7 cites·25 claims
- 2072US7765409B2Modular BIOS update mechanismINTEL CORP·Filed 2007·Granted Jul 27, 2010·6 cites·26 claims
- 2166US6591352B2Method and apparatus for executing firmware from a valid startup blockINTEL CORP·Filed 2001·Granted Jul 8, 2003·14 cites·20 claims
- 2262US7107405B2Writing cached data to system management memoryINTEL CORP·Filed 2003·Granted Sep 12, 2006·10 cites·21 claims
- 2360US8601227B2Methods and apparatus for demand-based memory mirroringSWANSON ROBERT C·Filed 2011·Granted Dec 3, 2013·1 cites·26 claims
- 2456US8843732B2Mechanism for detecting a no-processor swap condition and modification of high speed bus calibration during bootNATU MAHESH S·Filed 2009·Granted Sep 23, 2014·1 cites·17 claims
- 2552US12321622B2Deferred ECC (error checking and correction) memory initialization by memory scrub hardwareINTEL CORP·Filed 2021·Granted Jun 3, 2025·0 cites·16 claims
- 2648US10552643B2Fast boot up memory controllerINTEL CORP·Filed 2016·Granted Feb 4, 2020·0 cites·24 claims
- 2747US6564317B1Method and apparatus for securing computer firmware wherein unlocking of nonvolatile memory is prohibited unless address line masking Is disabled during an initialization eventINTEL CORP·Filed 1999·Granted May 13, 2003·20 cites·15 claims
- 2841US2018181504A1Apparatuses and methods for training one or more signal timing relations of a memory interfaceINTEL CORP·Filed 2016·Application pending·0 cites
- 2939US2002178352A1Firmware upgrade using address conversionFiled 2001·Application pending·0 cites
- 3034US2017168747A1Intelligent memory support for platform reset operationINTEL CORP·Filed 2015·Application pending·0 cites
- 3127US2018188959A1Memory Module With Integrated TrainingTHAKKAR SHACHI K·Filed 2016·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →