Inventor · disambiguated record
John R. Nickolls
Also filed as: NICKOLLS JOHN R
66 granted patents·3 pending applications·2,461 citations·filing 1990–2017
99Inventor score
Top patents by PatentIndex Score
69 records- 0199US7861060B1Parallel data processing systems and methods using cooperative thread arrays and thread identifier values to determine processing behaviorNVIDIA CORP·Filed 2005·Granted Dec 28, 2010·218 cites·18 claims
- 0298US7788468B1Synchronization of threads in a cooperative thread arrayNVIDIA CORP·Filed 2005·Granted Aug 31, 2010·169 cites·18 claims
- 0398US7627723B1Atomic memory operators in a parallel processorNVIDIA CORP·Filed 2006·Granted Dec 1, 2009·167 cites·20 claims
- 0497US7680988B1Single interconnect providing read and write access to a memory shared by concurrent threadsNVIDIA CORP·Filed 2006·Granted Mar 16, 2010·101 cites·21 claims
- 0597US7526634B1Counter-based delay of dependent thread group executionNVIDIA CORP·Filed 2006·Granted Apr 28, 2009·86 cites·18 claims
- 0696US8321849B2Virtual architecture and instruction set for parallel thread computingNICKOLLS JOHN R·Filed 2007·Granted Nov 27, 2012·88 cites·23 claims
- 0796US8108625B1Shared memory with parallel access and access conflict resolution mechanismCOON BRETT W·Filed 2006·Granted Jan 31, 2012·73 cites·19 claims
- 0895US9519947B2Architecture and instructions for accessing multi-dimensional formatted surface memoryNICKOLLS JOHN R·Filed 2010·Granted Dec 13, 2016·33 cites·27 claims
- 0995US7877585B1Structured programming control flow in a SIMD architectureNVIDIA CORP·Filed 2007·Granted Jan 25, 2011·47 cites·20 claims
- 1095US7761697B1Processing an indirect branch instruction in a SIMD architectureNVIDIA CORP·Filed 2006·Granted Jul 20, 2010·52 cites·20 claims
- 1195US7634621B1Register file allocationNVIDIA CORP·Filed 2006·Granted Dec 15, 2009·45 cites·24 claims
- 1295US7600155B1Apparatus and method for monitoring and debugging a graphics processing unitNVIDIA CORP·Filed 2005·Granted Oct 6, 2009·51 cites·20 claims
- 1394US8112614B2Parallel data processing systems and methods using cooperative thread arrays with unique thread identifiers as an input to compute an identifier of a location in a shared memoryNICKOLLS JOHN R·Filed 2010·Granted Feb 7, 2012·22 cites·17 claims
- 1494US7711990B1Apparatus and method for debugging a graphics processing unit in response to a debug instructionNVIDIA CORP·Filed 2005·Granted May 4, 2010·42 cites·17 claims
- 1594US7584342B1Parallel data processing systems and methods using cooperative thread arrays and SIMD instruction issueNVIDIA CORP·Filed 2005·Granted Sep 1, 2009·105 cites·24 claims
- 1693US7836116B1Fast fourier transforms and related transforms using cooperative thread arraysNVIDIA CORP·Filed 2006·Granted Nov 16, 2010·43 cites·20 claims
- 1792US8176265B2Shared single-access memory with management of multiple parallel requestsCOON BRETT W·Filed 2011·Granted May 8, 2012·16 cites·8 claims
- 1891US7937567B1Methods for scalably exploiting parallelism in a parallel processing systemNVIDIA CORP·Filed 2006·Granted May 3, 2011·22 cites·18 claims
- 1991US7640284B1Bit reversal methods for a parallel processorNVIDIA CORP·Filed 2006·Granted Dec 29, 2009·33 cites·17 claims
- 2090US10365930B2Instructions for managing a parallel cache hierarchyNVIDIA CORP·Filed 2017·Granted Jul 30, 2019·5 cites·14 claims
- 2190US8732713B2Thread group scheduler for computing on a parallel thread processorCOON BRETT W·Filed 2011·Granted May 20, 2014·15 cites·20 claims
- 2290US8700877B2Address mapping for a parallel thread processorSHEBANOW MICHAEL C·Filed 2010·Granted Apr 15, 2014·16 cites·20 claims
- 2389US9952977B2Cache operations and policies for a multi-threaded clientHEINRICH STEVEN JAMES·Filed 2010·Granted Apr 24, 2018·21 cites·25 claims
- 2489US8392669B1Systems and methods for coalescing memory accesses of parallel threadsNYLAND LARS·Filed 2008·Granted Mar 5, 2013·29 cites·23 claims
- 2589US7313583B2Galois field arithmetic unit for use within a processorBROADCOM CORP·Filed 2003·Granted Dec 25, 2007·72 cites·7 claims
- 2688US8055856B2Lock mechanism to enable atomic updates to shared memoryNVIDIA CORP·Filed 2008·Granted Nov 8, 2011·16 cites·18 claims
- 2788US7865894B1Distributing processing tasks within a processorNVIDIA CORP·Filed 2005·Granted Jan 4, 2011·19 cites·10 claims
- 2887US6959378B2Reconfigurable processing system and methodBROADCOM CORP·Filed 2001·Granted Oct 25, 2005·54 cites·35 claims
- 2987US5598408AScalable processor to processor and processor to I/O interconnection network and method for parallel processing arraysMASPAR COMPUTER CORP·Filed 1994·Granted Jan 28, 1997·124 cites·29 claims
- 3087US5280474AScalable processor to processor and processor-to-I/O interconnection network and method for parallel processing arraysMASPAR COMPUTER CORP·Filed 1990·Granted Jan 18, 1994·140 cites·11 claims
- 3186US5243699AInput/output system for parallel processing arraysMASPAR COMPUTER CORP·Filed 1991·Granted Sep 7, 1993·130 cites·22 claims
- 3285US9639365B2Indirect function call instructions in a synchronous parallel thread processorNVIDIA CORP·Filed 2012·Granted May 2, 2017·7 cites·22 claims
- 3385US8751771B2Efficient implementation of arrays of structures on SIMT and SIMD architecturesFAHS BRIAN·Filed 2011·Granted Jun 10, 2014·9 cites·20 claims
- 3484US9223578B2Coalescing memory barrier operations across multiple parallel threadsNICKOLLS JOHN R·Filed 2010·Granted Dec 29, 2015·8 cites·21 claims
- 3584US8312254B2Indirect function call instructions in a synchronous parallel thread processorCOON BRETT W·Filed 2008·Granted Nov 13, 2012·11 cites·16 claims
- 3684US6879207B1Defect tolerant redundancyNVIDIA CORP·Filed 2003·Granted Apr 12, 2005·30 cites·21 claims
- 3783US8615541B2Extended-precision integer arithmetic and logical instructionsJOHNSON RICHARD CRAIG·Filed 2010·Granted Dec 24, 2013·9 cites·21 claims
- 3883US8200947B1Systems and methods for voting among parallel threadsNICKOLLS JOHN R·Filed 2008·Granted Jun 12, 2012·11 cites·17 claims
- 3982US8615646B2Unanimous branch instructions in a parallel thread processorNICKOLLS JOHN R·Filed 2010·Granted Dec 24, 2013·6 cites·21 claims
- 4081US9830197B2Cooperative thread array reduction and scan operationsNVIDIA CORP·Filed 2016·Granted Nov 28, 2017·2 cites·20 claims
- 4181US8375176B2Lock mechanism to enable atomic updates to shared memoryNVIDIA CORP·Filed 2011·Granted Feb 12, 2013·5 cites·17 claims
- 4279US8522000B2Trap handler architecture for a parallel processing unitSHEBANOW MICHAEL C·Filed 2009·Granted Aug 27, 2013·11 cites·20 claims
- 4378US7027062B2Register based queuing for texture requestsNVIDIA CORP·Filed 2004·Granted Apr 11, 2006·18 cites·7 claims
- 4477US8086806B2Systems and methods for coalescing memory accesses of parallel threadsNYLAND LARS·Filed 2008·Granted Dec 27, 2011·10 cites·23 claims
- 4576US8271763B2Unified addressing and instructions for accessing parallel memory spacesNICKOLLS JOHN R·Filed 2009·Granted Sep 18, 2012·7 cites·20 claims
- 4676US7809928B1Generating event signals for performance register control using non-operative instructionsNVIDIA CORP·Filed 2005·Granted Oct 5, 2010·8 cites·18 claims
- 4775US10360039B2Predicted instruction execution in parallel processors with reduced per-thread state information including choosing a minimum or maximum of two operands based on a predicate valueJOHNSON RICHARD CRAIG·Filed 2010·Granted Jul 23, 2019·5 cites·16 claims
- 4874US8677106B2Unanimous branch instructions in a parallel thread processorNICKOLLS JOHN R·Filed 2010·Granted Mar 18, 2014·3 cites·20 claims
- 4974US7456835B2Register based queuing for texture requestsNVIDIA CORP·Filed 2006·Granted Nov 25, 2008·5 cites·21 claims
- 5074US5542074AParallel processor system with highly flexible local control capability, including selective inversion of instruction signal and control of bit shift amountMASPAR COMPUTER CORP·Filed 1992·Granted Jul 30, 1996·66 cites·10 claims
Showing the top 50 of 69 patent records by PatentIndex Score.
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