Inventor · disambiguated record
Jorge Parra
Also filed as: PARRA JORGE · PARRA JORGE E
37 granted patents·15 pending applications·129 citations·filing 2013–2025
96Inventor score
Top patents by PatentIndex Score
52 records- 0198US12007935B2Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point formatINTEL CORP·Filed 2020·Granted Jun 11, 2024·11 cites·25 claims
- 0298US11709793B2Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point formatINTEL CORP·Filed 2022·Granted Jul 25, 2023·9 cites·16 claims
- 0398US11361496B2Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point formatINTEL CORP·Filed 2021·Granted Jun 14, 2022·41 cites·23 claims
- 0497US11954063B2Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point formatINTEL CORP·Filed 2023·Granted Apr 9, 2024·2 cites·23 claims
- 0597US11182337B1Computing efficient cross channel operations in parallel computing machines using systolic arraysINTEL CORP·Filed 2020·Granted Nov 23, 2021·9 cites·20 claims
- 0696US11204977B2Scalable sparse matrix multiply acceleration using systolic arrays with feedback inputsINTEL CORP·Filed 2020·Granted Dec 21, 2021·7 cites·20 claims
- 0794US11636174B2Scalable sparse matrix multiply acceleration using systolic arrays with feedback inputsINTEL CORP·Filed 2021·Granted Apr 25, 2023·3 cites·20 claims
- 0893US10360654B1Software scoreboard information and synchronizationINTEL CORP·Filed 2018·Granted Jul 23, 2019·16 cites·20 claims
- 0990US2024362180A1Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point formatINTEL CORP·Filed 2024·Application pending·0 cites
- 1089US11977885B2Utilizing structured sparsity in systolic arraysINTEL CORP·Filed 2020·Granted May 7, 2024·2 cites·20 claims
- 1187US9032099B1Writeback mechanisms for improving far memory utilization in multi-level memory architecturesPARRA JORGE E·Filed 2013·Granted May 12, 2015·15 cites·20 claims
- 1285US11669490B2Computing efficient cross channel operations in parallel computing machines using systolic arraysINTEL CORP·Filed 2021·Granted Jun 6, 2023·1 cites·20 claims
- 1384US11042370B2Instruction and logic for systolic dot product with accumulateINTEL CORP·Filed 2018·Granted Jun 22, 2021·3 cites·20 claims
- 1483US12346694B2Register file for systolic arrayINTEL CORP·Filed 2021·Granted Jul 1, 2025·1 cites·20 claims
- 1582US12189571B2Dual pipeline parallel systolic arrayINTEL CORP·Filed 2021·Granted Jan 7, 2025·1 cites·20 claims
- 1682US11221848B2Sharing register file usage between fused processing resourcesINTEL CORP·Filed 2019·Granted Jan 11, 2022·3 cites·21 claims
- 1781US11294670B2Method and apparatus for performing reduction operations on a plurality of associated data element valuesINTEL CORP·Filed 2019·Granted Apr 5, 2022·2 cites·18 claims
- 1880US12405787B2Utilizing structured sparsity in systolic arraysINTEL CORP·Filed 2024·Granted Sep 2, 2025·0 cites·20 claims
- 1980US2025199863A1Using sparsity metadata to reduce systolic array power consumptionINTEL CORP·Filed 2024·Application pending·0 cites
- 2079US2024427847A1Scalable sparse matrix multiply acceleration using systolic arrays with feedback inputsINTEL CORP·Filed 2024·Application pending·0 cites
- 2177US12039001B2Scalable sparse matrix multiply acceleration using systolic arrays with feedback inputsINTEL CORP·Filed 2023·Granted Jul 16, 2024·0 cites·20 claims
- 2277US2025390307A1Register file for systolic arrayINTEL CORP·Filed 2025·Application pending·0 cites
- 2375US12093213B2Computing efficient cross channel operations in parallel computing machines using systolic arraysINTEL CORP·Filed 2023·Granted Sep 17, 2024·0 cites·20 claims
- 2475US2025117360A1Systolic array of arbitrary physical and logical depthINTEL CORP·Filed 2024·Application pending·0 cites
- 2575US2024053985A1Sharing register file usage between fused processing resourcesINTEL CORP·Filed 2023·Application pending·0 cites
- 2673US2025117359A1Dual pipeline parallel systolic arrayINTEL CORP·Filed 2024·Application pending·0 cites
- 2772US12430128B2Sharing register file usage between fused processing resourcesINTEL CORP·Filed 2022·Granted Sep 30, 2025·0 cites·18 claims
- 2872US2023297373A1Instruction and logic for systolic dot product with accumulateINTEL CORP·Filed 2023·Application pending·0 cites
- 2971US11900502B2Compiler assisted register file write reductionINTEL CORP·Filed 2022·Granted Feb 13, 2024·0 cites·20 claims
- 3071US10983794B2Register sharing mechanismINTEL CORP·Filed 2019·Granted Apr 20, 2021·1 cites·21 claims
- 3169US11640297B2Instruction and logic for systolic dot product with accumulateINTEL CORP·Filed 2021·Granted May 2, 2023·0 cites·20 claims
- 3268US12008067B2Sparse matrix multiplication acceleration mechanismINTEL CORP·Filed 2021·Granted Jun 11, 2024·0 cites·20 claims
- 3368US2022229661A1Method and apparatus for performing reduction operations on a plurality of associated data element valuesINTEL CORP·Filed 2022·Application pending·0 cites
- 3467US12190158B2Using sparsity metadata to reduce systolic array power consumptionINTEL CORP·Filed 2021·Granted Jan 7, 2025·0 cites·20 claims
- 3567US12174783B2Systolic array of arbitrary physical and logical depthINTEL CORP·Filed 2021·Granted Dec 24, 2024·0 cites·20 claims
- 3667US11188618B2Sparse matrix multiplication acceleration mechanismINTEL CORP·Filed 2019·Granted Nov 30, 2021·1 cites·19 claims
- 3767US9680652B2Dynamic heterogeneous hashing functions in ranges of system memory addressing spaceINTEL CORP·Filed 2016·Granted Jun 13, 2017·1 cites·20 claims
- 3866US11669329B2Instructions and logic for vector multiply add with zero skippingINTEL CORP·Filed 2022·Granted Jun 6, 2023·0 cites·20 claims
- 3964US12399685B2Systolic array having support for output sparsityINTEL CORP·Filed 2021·Granted Aug 26, 2025·0 cites·20 claims
- 4062US11321799B2Compiler assisted register file write reductionINTEL CORP·Filed 2019·Granted May 3, 2022·0 cites·26 claims
- 4162US11314515B2Instructions and logic for vector multiply add with zero skippingINTEL CORP·Filed 2019·Granted Apr 26, 2022·0 cites·20 claims
- 4259US10692170B2Software scoreboard information and synchronizationINTEL CORP·Filed 2019·Granted Jun 23, 2020·0 cites·20 claims
- 4354US10839478B2Accumulator pooling mechanismINTEL CORP·Filed 2019·Granted Nov 17, 2020·0 cites·22 claims
- 4453US11327754B2Method and apparatus for approximation using polynomialsINTEL CORP·Filed 2019·Granted May 10, 2022·0 cites·20 claims
- 4551US10817297B2Method and apparatus for vector-matrix comparisonINTEL CORP·Filed 2019·Granted Oct 27, 2020·0 cites·20 claims
- 4650US9424209B2Dynamic heterogeneous hashing functions in ranges of system memory addressing spacePARRA JORGE E·Filed 2013·Granted Aug 23, 2016·0 cites·23 claims
- 4749US2024111534A1Deterministic broadcasting from shared memoryINTEL CORP·Filed 2022·Application pending·0 cites
- 4849US2024111826A1Hardware enhancements for double precision systolic supportINTEL CORP·Filed 2022·Application pending·0 cites
- 4949US2024112295A1Shared local registers for thread team processingINTEL CORP·Filed 2022·Application pending·0 cites
- 5047US2016174545A1Closed System Cryopreservation DeviceBIOTECH INC·Filed 2014·Application pending·0 cites
Showing the top 50 of 52 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →