Inventor · disambiguated record
Jochen Preiss
Also filed as: PREISS JOCHEN
19 granted patents·3 pending applications·115 citations·filing 2005–2013
92Inventor score
Top patents by PatentIndex Score
22 records- 0192US7694112B2Multiplexing output from second execution unit add/saturation processing portion of wider width intermediate result of first primitive execution unit for compound computationIBM·Filed 2008·Granted Apr 6, 2010·37 cites·2 claims
- 0290US7461117B2Floating point unit with fused multiply add and method for calculating a result with a floating point unitIBM·Filed 2005·Granted Dec 2, 2008·30 cites·1 claims
- 0379US8291003B2Supporting multiple formats in a floating point processorBOERSMA MAARTEN J·Filed 2008·Granted Oct 16, 2012·11 cites·3 claims
- 0477US8578196B2Zero indication forwarding for floating point unit power reductionBAROWSKI HARRY S·Filed 2012·Granted Nov 5, 2013·3 cites·14 claims
- 0576US8244783B2Normalizer shift prediction for log estimate instructionsBOERSMA MAARTEN J·Filed 2008·Granted Aug 14, 2012·8 cites·12 claims
- 0672US7996738B2Semiconductor chip with a plurality of scannable storage elements and a method for scanning storage elements on a semiconductor chipIBM·Filed 2008·Granted Aug 9, 2011·7 cites·20 claims
- 0771US8346828B2System and method for storing numbers in first and second formats in a register fileIBM·Filed 2008·Granted Jan 1, 2013·5 cites·20 claims
- 0869US8407275B2Fast floating point compare with slower backup for corner casesBOERSMA MAARTEN J·Filed 2008·Granted Mar 26, 2013·4 cites·20 claims
- 0965US8255726B2Zero indication forwarding for floating point unit power reductionBAROWSKI HARRY S·Filed 2008·Granted Aug 28, 2012·3 cites·14 claims
- 1060US8352531B2Efficient forcing of corner cases in a floating point rounderIBM·Filed 2008·Granted Jan 8, 2013·2 cites·13 claims
- 1158US8566383B2Distributed residue-checking of a floating point unitDAO SON TRONG·Filed 2008·Granted Oct 22, 2013·3 cites·13 claims
- 1253US8032854B23-stack floorplan for floating point unitIBM·Filed 2008·Granted Oct 4, 2011·0 cites·8 claims
- 1351US8756263B2Binary logic unit and method to operate a binary logic unitIBM·Filed 2013·Granted Jun 17, 2014·0 cites·5 claims
- 1451US7735038B2Design structure to reduce power consumption within a clock gated synchronous circuit and clock gated synchronous circuitIBM·Filed 2007·Granted Jun 8, 2010·1 cites·7 claims
- 1551US7639046B2Method to reduce power consumption within a clock gated synchronous circuit and clock gated synchronous circuitIBM·Filed 2007·Granted Dec 29, 2009·1 cites·12 claims
- 1648US8452824B2Binary logic unit and method to operate a binary logic unitGEMMEKE TOBIAS·Filed 2007·Granted May 28, 2013·0 cites·4 claims
- 1747US8370409B2Electronic computing circuit for operand width reduction for a modulo adder followed by saturation concurrent message processingIBM·Filed 2008·Granted Feb 5, 2013·0 cites·7 claims
- 1847US2009198758A1Method for sign-extension in a multi-precision multiplierIBM·Filed 2008·Application pending·0 cites
- 1943US8332453B2Shifter with all-one and all-zero detection using a portion of partially shifted vector and shift amount in parallel to generated shifted resultBOERSMA MAARTEN·Filed 2008·Granted Dec 11, 2012·0 cites·15 claims
- 2042US2007050435A1Leading-Zero Counter and Method to Count Leading ZerosJACOBI CHRISTIAN·Filed 2006·Application pending·0 cites
- 2142US2007038693A1Method and Processor for Performing a Floating-Point Instruction Within a ProcessorJACOBI CHRISTIAN·Filed 2006·Application pending·0 cites
- 2231US8626807B2Reuse of rounder for fixed conversion of log instructionsBOERSMA MAARTEN·Filed 2009·Granted Jan 7, 2014·0 cites·17 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →