Inventor · disambiguated record
Joseph H. Salmon
Also filed as: SALMON JOSEPH H · SALMON JOSEPH HAROLD
27 granted patents·1 pending application·569 citations·filing 1989–2012
97Inventor score
Top patents by PatentIndex Score
28 records- 0192US6421801B1Testing IO timing in a delay locked system using separate transmit and receive loopsINTEL CORP·Filed 1999·Granted Jul 16, 2002·98 cites·20 claims
- 0289US5057715ACMOS output circuit using a low threshold deviceINTEL CORP·Filed 1989·Granted Oct 15, 1991·42 cites·1 claims
- 0388US8533538B2Method and apparatus for training a memory signal via an error signal of a memoryCHAUDHURI SANTANU·Filed 2010·Granted Sep 10, 2013·15 cites·28 claims
- 0487US8595428B2Memory controller functionalities to support data swizzlingBAINS KULJIT S·Filed 2009·Granted Nov 26, 2013·16 cites·20 claims
- 0587US6885959B2Circuit and method for calibrating DRAM pullup Ron to pulldown RonINTEL CORP·Filed 2002·Granted Apr 26, 2005·35 cites·44 claims
- 0684US7194559B2Slave I/O driver calibration using error-nulling master referenceINTEL CORP·Filed 2002·Granted Mar 20, 2007·38 cites·14 claims
- 0782US5077738ATest mode enable scheme for memoryINTEL CORP·Filed 1991·Granted Dec 31, 1991·49 cites·15 claims
- 0880US6941484B2Synthesis of a synchronization clockINTEL CORP·Filed 2002·Granted Sep 6, 2005·29 cites·30 claims
- 0979US5216289AAsynchronous reset scheme for ultra-low noise port tri-state output driver circuitINTEL CORP·Filed 1991·Granted Jun 1, 1993·36 cites·5 claims
- 1072US8132074B2Reliability, availability, and serviceability solutions for memory technologyBAINS KULJIT S·Filed 2007·Granted Mar 6, 2012·4 cites·23 claims
- 1165US5170073AUltra-low noise port output driver circuitINTEL CORP·Filed 1991·Granted Dec 8, 1992·18 cites·14 claims
- 1261US5892377AMethod and apparatus for reducing leakage currents in an I/O bufferINTEL CORP·Filed 1996·Granted Apr 6, 1999·16 cites·14 claims
- 1358US6236250B1Circuit for independent power-up sequencing of a multi-voltage chipINTEL CORP·Filed 1999·Granted May 22, 2001·15 cites·14 claims
- 1458US5574857AError detection circuit for power up initialization of a memory arrayINTEL CORP·Filed 1994·Granted Nov 12, 1996·18 cites·18 claims
- 1557US5298807ABuffer circuitry for transferring signals from TTL circuitry to dual range CMOS circuitryINTEL CORP·Filed 1991·Granted Mar 29, 1994·17 cites·5 claims
- 1655US5159672ABurst EPROM architectureINTEL CORP·Filed 1989·Granted Oct 27, 1992·24 cites·9 claims
- 1753US6381722B1Method and apparatus for testing high speed input pathsINTEL CORP·Filed 1999·Granted Apr 30, 2002·16 cites·21 claims
- 1853US5490109AMethod and apparatus for preventing over-erasure of flash EEPROM memory devicesINTEL CORP·Filed 1994·Granted Feb 6, 1996·15 cites·11 claims
- 1952US8392796B2Reliability, availability, and serviceability solution for memory technologyBAINS KULJIT S·Filed 2012·Granted Mar 5, 2013·0 cites·18 claims
- 2049US5243700APort expander architecture for mapping a first set of addresses to external memory and mapping a second set of addresses to an I/O portLARSEN ROBERT E·Filed 1992·Granted Sep 7, 1993·25 cites·14 claims
- 2147US6195759B1Method and apparatus for operating a synchronous strobe busINTEL CORP·Filed 1997·Granted Feb 27, 2001·19 cites·37 claims
- 2245US6973603B2Method and apparatus for optimizing timing for a multi-drop busINTEL CORP·Filed 2002·Granted Dec 6, 2005·3 cites·18 claims
- 2340US7117401B2Method and apparatus for optimizing timing for a multi-drop busINTEL CORP·Filed 2005·Granted Oct 3, 2006·0 cites·20 claims
- 2438US5379249AUPROM programming protect circuitINTEL CORP·Filed 1994·Granted Jan 3, 1995·6 cites·3 claims
- 2537US5257221AApparatus for selecting mumber of wait states in a burst EPROM architectureINTEL CORP·Filed 1992·Granted Oct 26, 1993·6 cites·6 claims
- 2635US2008151591A1Memory system with a configurable number of read data bitsINTEL CORP·Filed 2006·Application pending·0 cites
- 2733US5533196AMethod and apparatus for testing for a sufficient write voltage level during power up of a SRAM arrayINTEL CORP·Filed 1994·Granted Jul 2, 1996·3 cites·20 claims
- 2829US6260105B1Memory controller with a plurality of memory address busesINTEL CORP·Filed 1997·Granted Jul 10, 2001·6 cites·22 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →