Inventor · disambiguated record
Joseph S. Schibinger
Also filed as: SCHIBINGER JOSEPH S
14 granted patents·4 pending applications·443 citations·filing 1982–2006
94Inventor score
Technology areasG06F
Top patents by PatentIndex Score
18 records- 0181US4466061AConcurrent processing elements for using dependency free codeBURROUGHS CORP·Filed 1982·Granted Aug 14, 1984·61 cites·10 claims
- 0276US7213109B1System and method for providing speculative ownership of cached data based on history trackingUNISYS CORP·Filed 2002·Granted May 1, 2007·23 cites·28 claims
- 0374US4468736AMechanism for creating dependency free code for multiple processing elementsBURROUGHS CORP·Filed 1982·Granted Aug 28, 1984·45 cites·10 claims
- 0472US6092156ASystem and method for avoiding deadlocks utilizing split lock operations to provide exclusive access to memory during non-atomic operationsUNISYS CORP·Filed 1997·Granted Jul 18, 2000·56 cites·25 claims
- 0566US6457101B1System and method for providing the speculative return of cached data within a hierarchical memory systemUNISYS CORP·Filed 1999·Granted Sep 24, 2002·52 cites·20 claims
- 0664US7325082B1System and method for guaranteeing transactional fairness among multiple requestersUNISYS CORP·Filed 2004·Granted Jan 29, 2008·11 cites·22 claims
- 0763US6389515B1System and method for avoiding deadlocks utilizing split lock operations to provide exclusive access to memory during non-atomic operationsUNISYS CORP·Filed 2000·Granted May 14, 2002·8 cites·20 claims
- 0861US6477620B1Cache-level return data by-pass system for a hierarchical memoryUNISYS CORP·Filed 1999·Granted Nov 5, 2002·41 cites·20 claims
- 0960US6049845ASystem and method for providing speculative arbitration for transferring dataUNISYS CORP·Filed 1997·Granted Apr 11, 2000·39 cites·9 claims
- 1060US5321644AMethod and apparatus for division error detectionUNISYS CORP·Filed 1992·Granted Jun 14, 1994·34 cites·12 claims
- 1152US4819150AArray for simulating computer functions for large computer systemsUNISYS CORP·Filed 1985·Granted Apr 4, 1989·23 cites·11 claims
- 1250US5280615AOut of order job processing method and apparatusUNISYS CORP·Filed 1991·Granted Jan 18, 1994·25 cites·18 claims
- 1347US2007079074A1Tracking cache coherency in an extended multiple processor environmentCOLLIER JOSH D·Filed 2006·Application pending·0 cites
- 1447US2007079072A1Preemptive eviction of cache lines from a directoryCOLLIER JOSH D·Filed 2006·Application pending·0 cites
- 1547US2007233932A1Dynamic presence vector scaling in a coherency directoryCOLLIER JOSH D·Filed 2006·Application pending·0 cites
- 1647US2007079075A1Providing cache coherency in an extended multiple processor environmentCOLLIER JOSH D·Filed 2006·Application pending·0 cites
- 1744US5696936ALow latency message processor interface using memory mapped Read/Write WindowsUNISYS CORP·Filed 1995·Granted Dec 9, 1997·18 cites·12 claims
- 1834US4456958ASystem and method of renaming data items for dependency free codeBURROUGHS CORP·Filed 1982·Granted Jun 26, 1984·7 cites·10 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →