Inventor · disambiguated record
John J. Seliskar
Also filed as: SELISKAR JOHN J · SELISKAR JOHN JAMES
15 granted patents·728 citations·filing 1996–2012
95Inventor score
Top patents by PatentIndex Score
15 records- 0195US7211864B2Fully-depleted castellated gate MOSFET device and method of manufacture thereofSELISKAR JOHN J·Filed 2004·Granted May 1, 2007·136 cites·18 claims
- 0295US5985705ALow threshold voltage MOS transistor and method of manufactureLSI LOGIC CORP·Filed 1998·Granted Nov 16, 1999·148 cites·20 claims
- 0394US7968409B2Mixed-signal semiconductor platform incorporating fully-depleted castellated-gate MOSFET device and method of manufacture thereofSELISKAR JOHN J·Filed 2010·Granted Jun 28, 2011·20 cites·8 claims
- 0494US7714384B2Castellated gate MOSFET device capable of fully-depleted operationSELISKAR JOHN J·Filed 2007·Granted May 11, 2010·37 cites·7 claims
- 0592US6355532B1Subtractive oxidation method of fabricating a short-length and vertically-oriented channel, dual-gate, CMOS FETLSI LOGIC CORP·Filed 1999·Granted Mar 12, 2002·118 cites·37 claims
- 0690US6115233AIntegrated circuit device having a capacitor with the dielectric peripheral region being greater than the dielectric central regionLSI LOGIC CORP·Filed 1996·Granted Sep 5, 2000·78 cites·25 claims
- 0788US8138544B2Castellated gate MOSFET tetrode capable of fully-depleted operationSELISKAR JOHN JAMES·Filed 2010·Granted Mar 20, 2012·12 cites·8 claims
- 0886US7719058B2Mixed-signal semiconductor platform incorporating fully-depleted castellated-gate MOSFET device and method of manufacture thereofSELISKAR JOHN J·Filed 2005·Granted May 18, 2010·13 cites·13 claims
- 0986US7439139B2Fully-depleted castellated gate MOSFET device and method of manufacture thereofSELISKAR JOHN J·Filed 2007·Granted Oct 21, 2008·13 cites·22 claims
- 1079US5858828AUse of MEV implantation to form vertically modulated N+ buried layer in an NPN bipolar transistorSYMBIOS INC·Filed 1997·Granted Jan 12, 1999·48 cites·17 claims
- 1178US6316817B1MeV implantation to form vertically modulated N+ buried layer in an NPN bipolar transistorLSI LOGIC CORP·Filed 1998·Granted Nov 13, 2001·46 cites·20 claims
- 1274US6284586B1Integrated circuit device and method of making the same using chemical mechanical polishing to remove material in two layers following maskingLSI LOGIC CORP·Filed 1999·Granted Sep 4, 2001·29 cites·12 claims
- 1366US6525377B1Low threshold voltage MOS transistor and method of manufactureLSI LOGIC CORP·Filed 1999·Granted Feb 25, 2003·22 cites·13 claims
- 1445US8664071B2Castellated gate MOSFET tetrode capable of fully-depleted operationSELISKAR JOHN JAMES·Filed 2012·Granted Mar 4, 2014·0 cites·3 claims
- 1540US5780329AProcess for fabricating a moderate-depth diffused emitter bipolar transistor in a BICMOS device without using an additional maskSYMBIOS INC·Filed 1997·Granted Jul 14, 1998·8 cites·15 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →