Inventor · disambiguated record
Joshua P. Sinykin
Also filed as: SINYKIN JOSHUA P
9 granted patents·3 pending applications·8 citations·filing 2005–2012
79Inventor score
Top patents by PatentIndex Score
12 records- 0167US8745457B2Methods and structure for utilizing external interfaces used during normal operation of a circuit to output test signalsSAGHI EUGENE·Filed 2012·Granted Jun 3, 2014·2 cites·18 claims
- 0261US8589722B2Methods and structure for storing errors for error recovery in a hardware controllerSINYKIN JOSHUA P·Filed 2011·Granted Nov 19, 2013·2 cites·20 claims
- 0359US8271811B2Methods and apparatus for load-based power management of PHY logic circuits of a SAS device based upon a current workloadSINYKIN JOSHUA P·Filed 2009·Granted Sep 18, 2012·2 cites·18 claims
- 0458US8521931B2Serial input output (SIO) port expansion apparatus and methodSINYKIN JOSHUA P·Filed 2010·Granted Aug 27, 2013·1 cites·20 claims
- 0555US7636798B2Methods and systems for integrating unique information in SAS interface componentsLSI CORP·Filed 2009·Granted Dec 22, 2009·1 cites·5 claims
- 0646US7502874B2Methods and systems for integrating unique information in SAS interface componentsLSI CORP·Filed 2006·Granted Mar 10, 2009·0 cites·15 claims
- 0744US7493532B2Methods and structure for optimizing SAS domain link quality and performanceLSI CORP·Filed 2005·Granted Feb 17, 2009·0 cites·14 claims
- 0844US2011145452A1Methods and apparatus for distribution of raid storage management over a sas domainLSI CORP·Filed 2009·Application pending·0 cites
- 0941US8775888B2Methods and structure for correlating multiple test outputs of an integrated circuit acquired during separate instances of an eventSAGHI EUGENE·Filed 2012·Granted Jul 8, 2014·0 cites·20 claims
- 1041US8738979B2Methods and structure for correlation of test signals routed using different signaling pathwaysSMITH PAUL J·Filed 2012·Granted May 27, 2014·0 cites·20 claims
- 1137US2007121496A1System and method for amplitude optimization in high-speed serial transmissionsSINYKIN JOSHUA P·Filed 2005·Application pending·0 cites
- 1236US2013179741A1Mapping circuit test logic by analyzing register transfer level circuit modelsSINYKIN JOSHUA P·Filed 2012·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →