Inventor · disambiguated record
John Wiegert
Also filed as: WIEGERT JOHN · WIEGERT JOHN A
5 granted patents·20 pending applications·6 citations·filing 2001–2025
69Inventor score
Top patents by PatentIndex Score
25 records- 0192US12014183B2Base plus offset addressing for load/store messagesINTEL CORP·Filed 2022·Granted Jun 18, 2024·2 cites·20 claims
- 0279US12333310B2Base plus offset addressing for load/store messagesINTEL CORP·Filed 2024·Granted Jun 17, 2025·0 cites·20 claims
- 0379US2025348321A1Base plus offset addressing for load/store messagesINTEL CORP·Filed 2025·Application pending·0 cites
- 0472US2025130848A1Barrier state save and restore for preemption in a graphics environmentINTEL CORP·Filed 2024·Application pending·0 cites
- 0565US2025118003A1Exception handling for debugging in a graphics environmentINTEL CORP·Filed 2024·Application pending·0 cites
- 0663US12164952B2Barrier state save and restore for preemption in a graphics environmentINTEL CORP·Filed 2021·Granted Dec 10, 2024·0 cites·25 claims
- 0762US7581045B2Method, system, and article of manufacture for mapping programming interfacesINTEL CORP·Filed 2005·Granted Aug 25, 2009·4 cites·16 claims
- 0862US2025291756A1Graphics processor addressable barriersINTEL CORP·Filed 2024·Application pending·0 cites
- 0962US2025291755A1GPU Asynchronous Direct Memory Access ApplicationsINTEL CORP·Filed 2024·Application pending·0 cites
- 1061US2025292354A1Systolic array matrix accelerator for graphics processing unit applicationsINTEL CORP·Filed 2024·Application pending·0 cites
- 1158US2025291590A1Gpu asynchronous matrix multiply accumulate applicationsINTEL CORP·Filed 2024·Application pending·0 cites
- 1255US12154207B2Exception handling for debugging in a graphics environmentINTEL CORP·Filed 2021·Granted Nov 26, 2024·0 cites·25 claims
- 1355US2025147762A1Multiple register allocation sizes for gpu hardware threadsINTEL CORP·Filed 2023·Application pending·0 cites
- 1454US2025307155A1Apparatus and Method for Extended Cache Control for Workloads using Temporary or Scratch Memory SpaceINTEL CORP·Filed 2024·Application pending·0 cites
- 1554US2025231769A1Bindless thread dispatch mid-thread preemption on a graphics processorINTEL CORP·Filed 2024·Application pending·0 cites
- 1651US2024220335A1Synchronization for data multicast in compute core clustersINTEL CORP·Filed 2022·Application pending·0 cites
- 1751US2024220254A1Data multicast in compute core clustersINTEL CORP·Filed 2022·Application pending·0 cites
- 1850US2024231621A9Virtual address access to gpu surface and sampler statesINTEL CORP·Filed 2022·Application pending·0 cites
- 1949US2024231957A9Named and cluster barriersINTEL CORP·Filed 2022·Application pending·0 cites
- 2049US2024086064A1Offset scaling in load/store messagesINTEL CORP·Filed 2022·Application pending·0 cites
- 2148US2024160478A1Increasing processing resources in processing cores of a graphics environmentINTEL CORP·Filed 2022·Application pending·0 cites
- 2246US2024087077A1Merging atomics to the same cache lineINTEL CORP·Filed 2022·Application pending·0 cites
- 2339US2003058860A1Destination address filteringFiled 2001·Application pending·0 cites
- 2437US2007011358A1Mechanisms to implement memory management to enable protocol-aware asynchronous, zero-copy transmitsWIEGERT JOHN·Filed 2005·Application pending·0 cites
- 2536US2022413994A1Watchpoints for debugging in a graphics environmentINTEL CORP·Filed 2021·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →