Inventor · disambiguated record
Juergen Dirks
Also filed as: DIRKS JUERGEN
23 granted patents·4 pending applications·351 citations·filing 2002–2015
96Inventor score
Top patents by PatentIndex Score
27 records- 0198US7747975B2Timing violation debugging inside place and route toolLSI CORP·Filed 2007·Granted Jun 29, 2010·196 cites·21 claims
- 0290US7325215B2Timing violation debugging inside place and route toolLSI LOGIC CORP·Filed 2005·Granted Jan 29, 2008·21 cites·19 claims
- 0386US7398489B2Advanced standard cell power connectionLSI CORP·Filed 2005·Granted Jul 8, 2008·18 cites·21 claims
- 0479US7441210B2On-the-fly RTL instructor for advanced DFT and design closureLSI CORP·Filed 2005·Granted Oct 21, 2008·10 cites·20 claims
- 0577US7546568B2Automation of tie cell insertion, optimization and replacement by scan flip-flops to increase fault coverageLSI CORP·Filed 2005·Granted Jun 9, 2009·7 cites·18 claims
- 0675US8219959B2Generating integrated circuit floorplan layoutsDIRKS JUERGEN·Filed 2009·Granted Jul 10, 2012·7 cites·17 claims
- 0774US8539407B2Intelligent timing analysis and constraint generation GUIDIRKS JUERGEN·Filed 2009·Granted Sep 17, 2013·5 cites·14 claims
- 0874US7546560B2Optimization of flip flop initialization structures with respect to design size and design closure effort from RTL to netlistLSI CORP·Filed 2006·Granted Jun 9, 2009·8 cites·22 claims
- 0973US8584068B2Timing violation debugging inside place and route toolDINTER MATTHIAS·Filed 2010·Granted Nov 12, 2013·4 cites·20 claims
- 1073US7523426B2Intelligent timing analysis and constraint generation GUILSI CORP·Filed 2005·Granted Apr 21, 2009·5 cites·20 claims
- 1171US7000163B1Optimized buffering for JTAG boundary scan netsLSI LOGIC CORP·Filed 2002·Granted Feb 14, 2006·17 cites·16 claims
- 1267US8161447B2Automation of tie cell insertion, optimization and replacement by scan flip-flops to increase fault coverageDIRKS JUERGEN·Filed 2009·Granted Apr 17, 2012·3 cites·20 claims
- 1366US7191424B2Special tie-high/low cells for single metal layer route changesLSI LOGIC CORP·Filed 2004·Granted Mar 13, 2007·13 cites·23 claims
- 1463US7958473B2Method and computer program for configuring an integrated circuit design for static timing analysisLSI CORP·Filed 2008·Granted Jun 7, 2011·4 cites·12 claims
- 1562US8572543B2Automation of tie cell insertion, optimization and replacement by scan flip-flops to increase fault coverageDIRKS JUERGEN·Filed 2012·Granted Oct 29, 2013·1 cites·19 claims
- 1662US7331028B2Engineering change order scenario managerLSI LOGIC CORP·Filed 2004·Granted Feb 12, 2008·9 cites·23 claims
- 1758US8332801B2Special engineering change order cellsDIRKS JUERGEN·Filed 2009·Granted Dec 11, 2012·1 cites·18 claims
- 1857US7334206B2Cell builder for different layer stacksLSI LOGIC CORP·Filed 2004·Granted Feb 19, 2008·8 cites·20 claims
- 1956US8863053B2Intelligent timing analysis and constraint generation GUILSI CORP·Filed 2013·Granted Oct 14, 2014·0 cites·20 claims
- 2056US8564337B2Clock tree insertion delay independent interfaceBLOCK STEFAN·Filed 2011·Granted Oct 22, 2013·1 cites·20 claims
- 2156US7975197B2On-chip scan clock generator for ASIC testingLSI CORP·Filed 2003·Granted Jul 5, 2011·7 cites·16 claims
- 2252US7117472B2Placement of a clock signal supply network during design of integrated circuitsLSI LOGIC CORP·Filed 2004·Granted Oct 3, 2006·6 cites·20 claims
- 2347US7634748B2Special engineering change order cellsLSI CORP·Filed 2004·Granted Dec 15, 2009·0 cites·20 claims
- 2444US2007204215A1Device for analyzing log files generated by process automation toolsLSI LOGIC CORP·Filed 2006·Application pending·0 cites
- 2536US2011320997A1Delay-Cell Footprint-Compatible BuffersLABIB FARID·Filed 2010·Application pending·0 cites
- 2631US2011063926A1Write Through Speed Up for Memory CircuitLSI CORP·Filed 2009·Application pending·0 cites
- 2731US2016284392A1Memory cell, memory device including a plurality of memory cells and method including read and write operations at a memory cellGLOBALFOUNDRIES INC·Filed 2015·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →