Inventor · disambiguated record
Judy M. Gehman
Also filed as: GEHMAN JUDY · GEHMAN JUDY M
15 granted patents·2 pending applications·391 citations·filing 1998–2013
94Inventor score
Top patents by PatentIndex Score
17 records- 0195US7457905B2Method for request transaction ordering in OCP bus to AXI bus bridge designLSI CORP·Filed 2006·Granted Nov 25, 2008·52 cites·20 claims
- 0287US8095734B2Managing cache line allocations for multiple issue processorsLIPPERT GARY·Filed 2009·Granted Jan 10, 2012·26 cites·20 claims
- 0387US6073132APriority arbiter with shifting sequential priority schemeLSI LOGIC CORP·Filed 1998·Granted Jun 6, 2000·143 cites·32 claims
- 0484US7000092B2Heterogeneous multi-processor reference designLSI LOGIC CORP·Filed 2002·Granted Feb 14, 2006·40 cites·10 claims
- 0574US6496517B1Direct attach of interrupt controller to processor moduleLSI LOGIC CORP·Filed 2001·Granted Dec 17, 2002·20 cites·8 claims
- 0667US7620743B2System and method for implementing multiple instantiated configurable peripherals in a circuit designLSI CORP·Filed 2004·Granted Nov 17, 2009·13 cites·12 claims
- 0762US7949986B2Method for estimation of trace information bandwidth requirementsLSI CORP·Filed 2008·Granted May 24, 2011·2 cites·32 claims
- 0862US7584460B2Process and apparatus for abstracting IC design filesLSI CORP·Filed 2003·Granted Sep 1, 2009·12 cites·5 claims
- 0962US6785755B1Grant removal via dummy master arbitrationLSI LOGIC CORP·Filed 2001·Granted Aug 31, 2004·9 cites·20 claims
- 1060US6745273B1Automatic deadlock prevention via arbitration switchingLSI LOGIC CORP·Filed 2001·Granted Jun 1, 2004·11 cites·20 claims
- 1152US6304553B1Method and apparatus for processing data packetsLSI LOGIC CORP·Filed 1998·Granted Oct 16, 2001·29 cites·43 claims
- 1250US6260093B1Method and apparatus for arbitrating access to multiple buses in a data processing systemLSI LOGIC CORP·Filed 1998·Granted Jul 10, 2001·25 cites·32 claims
- 1349US9235521B2Cache system for managing various cache line conditionsLSI CORP·Filed 2013·Granted Jan 12, 2016·0 cites·20 claims
- 1444US2005229143A1System and method for implementing multiple instantiated configurable peripherals in a circuit designLSI LOGIC CORP·Filed 2004·Application pending·0 cites
- 1536US6115770ASystem and method for coordinating competing register accesses by multiple busesLSI LOGIC CORP·Filed 1998·Granted Sep 5, 2000·9 cites·34 claims
- 1636US2007150627A1Endian mapping engine, method of endian mapping and a processing system employing the engine and the methodLSI LOGIC CORP·Filed 2005·Application pending·0 cites
- 1735US8510493B2Circuit to efficiently handle data movement within a cache controller or on-chip memory peripheralGEHMAN JUDY M·Filed 2010·Granted Aug 13, 2013·0 cites·16 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →