Inventor · disambiguated record
Juergen Haess
Also filed as: HAESS JUERGEN · HAESS JUERGEN G · HAESS JUERGEN GEORG
24 granted patents·6 pending applications·134 citations·filing 1993–2018
94Inventor score
Top patents by PatentIndex Score
30 records- 0190US7461117B2Floating point unit with fused multiply add and method for calculating a result with a floating point unitIBM·Filed 2005·Granted Dec 2, 2008·30 cites·1 claims
- 0282US7730117B2System and method for a floating point unit with feedback prior to normalization and roundingIBM·Filed 2005·Granted Jun 1, 2010·13 cites·20 claims
- 0378US8352530B2Residue calculation with built-in correction in a floating point unit positioned at different levels using correction values provided by multiplexerIBM·Filed 2008·Granted Jan 8, 2013·9 cites·17 claims
- 0470US9977680B2Clock-gating for multicycle instructionsIBM·Filed 2016·Granted May 22, 2018·1 cites·17 claims
- 0568US7392273B2High-sticky calculation in pipelined fused multiply/add circuitryIBM·Filed 2003·Granted Jun 24, 2008·14 cites·3 claims
- 0666US7716266B2Common shift-amount calculation for binary and hex floating pointIBM·Filed 2006·Granted May 11, 2010·4 cites·10 claims
- 0766US5524270ASystem for transferring data between asynchronous data buses with a data buffer interposed in between the buses for synchronization of devices timed by different clocksIBM·Filed 1993·Granted Jun 4, 1996·46 cites·11 claims
- 0865US9513987B2Using error correcting codes for parity purposesIBM·Filed 2014·Granted Dec 6, 2016·2 cites·10 claims
- 0964US8984039B2Residue-based error detection for a processor execution unit that supports vector operationsBOERSMA MAARTEN JAKOB·Filed 2012·Granted Mar 17, 2015·2 cites·11 claims
- 1058US10310936B2Temporary pipeline marking for processor error workaroundsIBM·Filed 2017·Granted Jun 4, 2019·0 cites·15 claims
- 1158US9529664B2Using error correcting codes for parity purposesIBM·Filed 2014·Granted Dec 27, 2016·0 cites·5 claims
- 1258US8566383B2Distributed residue-checking of a floating point unitDAO SON TRONG·Filed 2008·Granted Oct 22, 2013·3 cites·13 claims
- 1357US10552167B2Clock-gating for multicycle instructionsIBM·Filed 2017·Granted Feb 4, 2020·0 cites·20 claims
- 1457US9575836B2Temporary pipeline marking for processor error workaroundsIBM·Filed 2016·Granted Feb 21, 2017·0 cites·1 claims
- 1556US9507659B2Temporary pipeline marking for processor error workaroundsIBM·Filed 2016·Granted Nov 29, 2016·0 cites·1 claims
- 1655US9170771B2Residue-based error detection for a processor execution unit that supports vector operationsIBM·Filed 2014·Granted Oct 27, 2015·0 cites·6 claims
- 1754US9588852B2Temporary pipeline marking for processor error workaroundsIBM·Filed 2015·Granted Mar 7, 2017·0 cites·15 claims
- 1854US8909994B2Dynamic hardware trace supporting multiphase operationsIBM·Filed 2013·Granted Dec 9, 2014·0 cites·13 claims
- 1953US11175921B2Cognitive binary coded decimal to binary number conversion hardware for evaluating a preferred instruction variant based on feedbackIBM·Filed 2018·Granted Nov 16, 2021·0 cites·18 claims
- 2053US2016357636A1Using error correcting codes for parity purposesIBM·Filed 2016·Application pending·0 cites
- 2153US2014164463A1Exponent flow checkingIBM·Filed 2014·Application pending·0 cites
- 2251US8892958B2Dynamic hardware trace supporting multiphase operationsCARLOUGH STEVEN R·Filed 2012·Granted Nov 18, 2014·0 cites·20 claims
- 2349US2013339417A1Residue-based exponent flow checkingHAESS JUERGEN·Filed 2012·Application pending·0 cites
- 2448US7085865B2I/O throughput by pre-termination arbitrationIBM·Filed 2004·Granted Aug 1, 2006·1 cites·20 claims
- 2543US7188233B2System and method for performing floating point store foldingIBM·Filed 2005·Granted Mar 6, 2007·0 cites·16 claims
- 2642US6694344B1Examination of residues of data-conversionsIBM·Filed 1999·Granted Feb 17, 2004·9 cites·14 claims
- 2742US2006179096A1System and method for a fused multiply-add dataflow with early feedback prior to roundingIBM·Filed 2005·Application pending·0 cites
- 2842US2006179286A1System and method for processing limited out-of-order execution of floating point loadsIBM·Filed 2005·Application pending·0 cites
- 2941US2006184603A1Zero detect in partial sums while addingTRONG SON D·Filed 2005·Application pending·0 cites
- 3038US10416962B2Decimal and binary floating point arithmetic calculationsIBM·Filed 2015·Granted Sep 17, 2019·0 cites·17 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →