Inventor · disambiguated record
Jun Sawada
Also filed as: SAWADA JUN
68 granted patents·18 pending applications·277 citations·filing 1990–2024
98Inventor score
Top patents by PatentIndex Score
86 records- 0197US10621489B2Massively parallel neural inference computing elementsIBM·Filed 2018·Granted Apr 14, 2020·30 cites·33 claims
- 0295US9244124B2Initializing and testing integrated circuits with selectable scan chains with exclusive-or outputsIBM·Filed 2014·Granted Jan 26, 2016·12 cites·20 claims
- 0391US9992057B2Yield tolerance in a neurosynaptic systemIBM·Filed 2014·Granted Jun 5, 2018·12 cites·20 claims
- 0487US9984324B2Dual deterministic and stochastic neurosynaptic core circuitIBM·Filed 2016·Granted May 29, 2018·6 cites·14 claims
- 0587US8181134B2Techniques for performing conditional sequential equivalence checking of an integrated circuit logic designBAUMGARTNER JASON R·Filed 2009·Granted May 15, 2012·15 cites·20 claims
- 0686US10454759B2Yield tolerance in a neurosynaptic systemIBM·Filed 2018·Granted Oct 22, 2019·3 cites·18 claims
- 0786US9940302B2Interconnect circuits at three dimensional (3-D) bonding interfaces of a processor arrayIBM·Filed 2016·Granted Apr 10, 2018·4 cites·20 claims
- 0885US9588937B2Array of processor core circuits with reversible tiersIBM·Filed 2013·Granted Mar 7, 2017·7 cites·20 claims
- 0984US9852006B2Consolidating multiple neurosynaptic core circuits into one reconfigurable memory block maintaining neuronal information for the core circuitsIBM·Filed 2014·Granted Dec 26, 2017·15 cites·20 claims
- 1082US10452540B2Memory-mapped interface for message passing computing systemsIBM·Filed 2017·Granted Oct 22, 2019·4 cites·27 claims
- 1181US8397187B2Verifying the error bound of numerical computation implemented in computer systemsSAWADA JUN·Filed 2010·Granted Mar 12, 2013·10 cites·20 claims
- 1280US10831595B1Performing error detection during deterministic program executionIBM·Filed 2019·Granted Nov 10, 2020·2 cites·20 claims
- 1379US12406186B2Conflict-free, stall-free, broadcast network on chipIBM·Filed 2020·Granted Sep 2, 2025·1 cites·21 claims
- 1479US9747545B2Self-timed, event-driven neurosynaptic core controllerIBM·Filed 2014·Granted Aug 29, 2017·9 cites·18 claims
- 1578US11537859B2Flexible precision neural inference processing unitIBM·Filed 2019·Granted Dec 27, 2022·3 cites·20 claims
- 1677US9924490B2Scaling multi-core neurosynaptic networks across chip boundariesIBM·Filed 2013·Granted Mar 20, 2018·7 cites·20 claims
- 1776US11521085B2Neural network weight distribution from a grid of memory elementsIBM·Filed 2020·Granted Dec 6, 2022·1 cites·24 claims
- 1876US10785745B2Scaling multi-core neurosynaptic networks across chip boundariesIBM·Filed 2017·Granted Sep 22, 2020·2 cites·18 claims
- 1975US11501140B2Runtime reconfigurable neural network processor coreIBM·Filed 2018·Granted Nov 15, 2022·2 cites·21 claims
- 2075US9558443B2Dual deterministic and stochastic neurosynaptic core circuitIBM·Filed 2013·Granted Jan 31, 2017·6 cites·20 claims
- 2174US12056598B2Runtime reconfigurable neural network processor coreIBM·Filed 2022·Granted Aug 6, 2024·0 cites·24 claims
- 2274US11270196B2Multi-mode low-precision inner-product computation circuits for massively parallel neural inference engineIBM·Filed 2019·Granted Mar 8, 2022·2 cites·20 claims
- 2374US6675182B1Method and apparatus for performing rotate operations using cascaded multiplexersIBM·Filed 2000·Granted Jan 6, 2004·21 cites·6 claims
- 2472US12387082B2Scheduler for mapping neural networks onto an array of neural cores in an inference processing unitIBM·Filed 2018·Granted Aug 12, 2025·2 cites·25 claims
- 2572US10410109B2Peripheral device interconnections for neurosynaptic systemsIBM·Filed 2014·Granted Sep 10, 2019·5 cites·20 claims
- 2672US5103739AApparatus for tracking an overhead line and automatically moving around obstacles on the lineTOKYO ELECTRIC POWER CO·Filed 1990·Granted Apr 14, 1992·41 cites·25 claims
- 2770US9886662B2Converting spike event data to digital numeric dataIBM·Filed 2014·Granted Feb 6, 2018·4 cites·20 claims
- 2869US7529371B2Replaceable sequenced one-time pads for detection of cloned service clientIBM·Filed 2004·Granted May 5, 2009·13 cites·12 claims
- 2968US10769519B2Converting digital numeric data to spike event dataIBM·Filed 2017·Granted Sep 8, 2020·1 cites·20 claims
- 3067US11238347B2Data distribution in an array of neural network coresIBM·Filed 2018·Granted Feb 1, 2022·1 cites·25 claims
- 3167US8229992B2Fused booth encoder multiplexerBELLUOMINI WENDY ANN·Filed 2007·Granted Jul 24, 2012·3 cites·10 claims
- 3266US12182687B2Data representation for dynamic precision in neural network coresIBM·Filed 2018·Granted Dec 31, 2024·1 cites·22 claims
- 3366US10102474B2Event-based neural network with hierarchical addressing for routing event packets between core circuits of the neural networkIBM·Filed 2014·Granted Oct 16, 2018·3 cites·20 claims
- 3464US11010662B2Massively parallel neural inference computing elementsIBM·Filed 2020·Granted May 18, 2021·0 cites·23 claims
- 3564US8756543B2Verifying data intensive state transition machines related applicationPARUTHI VIRESH·Filed 2011·Granted Jun 17, 2014·2 cites·20 claims
- 3663US9881252B2Converting digital numeric data to spike event dataIBM·Filed 2014·Granted Jan 30, 2018·2 cites·20 claims
- 3763US7272624B2Fused booth encoder multiplexerIBM·Filed 2003·Granted Sep 18, 2007·7 cites·9 claims
- 3862US11184221B2Yield tolerance in a neurosynaptic systemIBM·Filed 2019·Granted Nov 23, 2021·0 cites·20 claims
- 3960US10838860B2Memory-mapped interface to message-passing computing systemsIBM·Filed 2019·Granted Nov 17, 2020·0 cites·20 claims
- 4060US10650301B2Utilizing a distributed and parallel set of neurosynaptic core circuits for neuronal computation and non-neuronal computationIBM·Filed 2014·Granted May 12, 2020·2 cites·16 claims
- 4160US9601921B2Tie-off circuit with output node isolation for protection from electrostatic discharge (ESD) damageIBM·Filed 2013·Granted Mar 21, 2017·1 cites·20 claims
- 4259US10984307B2Peripheral device interconnections for neurosynaptic systemsIBM·Filed 2019·Granted Apr 20, 2021·0 cites·12 claims
- 4359US8397189B2Model checking in state transition machine verificationPARUTHI VIRESH·Filed 2011·Granted Mar 12, 2013·1 cites·20 claims
- 4458US9274751B2Fused booth encoder multiplexerBELLUOMINI WENDY ANN·Filed 2007·Granted Mar 1, 2016·1 cites·5 claims
- 4558US7249501B2Pressure distribution measurement systemHONDA MOTOR CO LTD·Filed 2005·Granted Jul 31, 2007·4 cites·24 claims
- 4657US9797946B2Initializing and testing integrated circuits with selectable scan chains with exclusive-OR outputsIBM·Filed 2015·Granted Oct 24, 2017·0 cites·18 claims
- 4756US12400112B2Efficient method for VLSI implementation of useful neural network activation functionsIBM·Filed 2020·Granted Aug 26, 2025·0 cites·17 claims
- 4855US11049001B2Event-based neural network with hierarchical addressing for routing event packets between core circuits of the neural networkIBM·Filed 2018·Granted Jun 29, 2021·0 cites·15 claims
- 4955US10929747B2Dual deterministic and stochastic neurosynaptic core circuitIBM·Filed 2018·Granted Feb 23, 2021·0 cites·20 claims
- 5055US10740282B2Interconnect circuits at three-dimensional (3-D) bonding interfaces of a processor arrayIBM·Filed 2018·Granted Aug 11, 2020·0 cites·14 claims
Showing the top 50 of 86 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →