Inventor · disambiguated record
Juing-Yi Wu
Also filed as: WU JUING-YI
23 granted patents·2 pending applications·54 citations·filing 1996–2024
93Inventor score
Files withTAIWAN SEMICONDUCTOR MFG CO LTD17TAIWAN SEMICONDUCTOR MFG5CHEN CHIN-AN1TAIWAN SEMICONDUCTOR MANFACTUR1TAIWAN SEMICONDUCTOR MANUAFACT1
Top patents by PatentIndex Score
25 records- 0191US9984191B2Cell layout and structureTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2014·Granted May 29, 2018·13 cites·20 claims
- 0287US10325849B2Different scaling ratio in FEOL/ MOL/ BEOLTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted Jun 18, 2019·4 cites·20 claims
- 0387US9292649B2Different scaling ratio in FEOL / MOL/ BEOLTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2013·Granted Mar 22, 2016·6 cites·20 claims
- 0487US9136168B2Conductive line patterningTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Sep 15, 2015·5 cites·20 claims
- 0586US2024371765A1Different scaling ratio in feol / mol/ beolTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Application pending·0 cites
- 0685US9047437B2Method, system and software for accessing design rules and library of design features while designing semiconductor device layoutTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2014·Granted Jun 2, 2015·8 cites·19 claims
- 0784US11152303B2Different scaling ratio in FEOL / MOL/ BEOLTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Oct 19, 2021·2 cites·20 claims
- 0881US9508791B2Semiconductor device having a metal gateTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted Nov 29, 2016·3 cites·20 claims
- 0976US12322701B2Different scaling ratio in FEOL / MOL/ BEOLTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Jun 3, 2025·0 cites·20 claims
- 1068US11281835B2Cell layout and structureTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Mar 22, 2022·0 cites·20 claims
- 1167US9746783B2Method for preventing photoresist corner rounding effectsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2013·Granted Aug 29, 2017·1 cites·20 claims
- 1265US10998304B2Conductive line patterningTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted May 4, 2021·0 cites·20 claims
- 1360US10664639B2Cell layout and structureTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Granted May 26, 2020·0 cites·20 claims
- 1459US10269785B2Conductive line patterningTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted Apr 23, 2019·0 cites·20 claims
- 1556US9472501B2Conductive line patterningTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted Oct 18, 2016·0 cites·20 claims
- 1655US8769475B2Method, system and software for accessing design rules and library of design features while designing semiconductor device layoutCHEN CHIN-AN·Filed 2011·Granted Jul 1, 2014·1 cites·18 claims
- 1754US9391056B2Mask optimization for multi-layer contactsTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Jul 12, 2016·0 cites·20 claims
- 1854US9087773B2Implant region definitionTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Jul 21, 2015·0 cites·20 claims
- 1954US7309897B2Electrostatic discharge protector for an integrated circuitTAIWAN SEMICONDUCTOR MANUAFACT·Filed 2006·Granted Dec 18, 2007·2 cites·17 claims
- 2050US10283495B2Mask optimization for multi-layer contactsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted May 7, 2019·0 cites·20 claims
- 2150US9637818B2Implant region definitionTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted May 2, 2017·0 cites·13 claims
- 2240US5895257ALOCOS field oxide and field oxide process using silicon nitride spacersTAIWAN SEMICONDUCTOR MANFACTUR·Filed 1996·Granted Apr 20, 1999·9 cites·18 claims
- 2337US10366900B2Semiconductor device and manufacturing method thereofTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted Jul 30, 2019·0 cites·20 claims
- 2437US2005258505A1Mixed implantation on polysilicon fuse for CMOS technologyTAIWAN SEMICONDUCTOR MFG·Filed 2004·Application pending·0 cites
- 2532US6936408B2Partially photoexposed positive photoresist layer blocking method for regio-selectively processing a microelectronic layerTAIWAN SEMICONDUCTOR MFG·Filed 2002·Granted Aug 30, 2005·0 cites·12 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →