Inventor · disambiguated record
Jye-Yen Cheng
Also filed as: CHENG JYE-YEN
37 granted patents·5 pending applications·173 citations·filing 1993–2025
97Inventor score
Files withTAIWAN SEMICONDUCTOR MFG CO LTD31TAIWAN SEMICONDUCTOR MFG4CHANG CHUNG-LONG1HO CHIEN-CHIH1HUA WEI-CHUN1
Top patents by PatentIndex Score
42 records- 0196US11424188B2Methods of fabricating integrated circuit devices having raised via contactsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Aug 23, 2022·3 cites·20 claims
- 0295US9653348B1Semiconductor device and manufacturing method thereofTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted May 16, 2017·23 cites·20 claims
- 0394US9397045B2Structure and formation method of damascene structureTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2014·Granted Jul 19, 2016·12 cites·20 claims
- 0491US10475703B2Structure and formation method of damascene structureTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Nov 12, 2019·5 cites·20 claims
- 0590US10840189B2Integrated circuit devices having raised via contacts and methods of fabricating the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Granted Nov 17, 2020·4 cites·20 claims
- 0689US7880303B2Stacked contact with low aspect ratioTAIWAN SEMICONDUCTOR MFG·Filed 2007·Granted Feb 1, 2011·16 cites·19 claims
- 0786US10157843B2Semiconductor device and manufacturing method thereofTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Dec 18, 2018·3 cites·20 claims
- 0886US9852992B2Semiconductor device and manufacturing method thereofTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Dec 26, 2017·3 cites·20 claims
- 0984US10879179B2Semiconductor device and manufacturing method thereofTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Granted Dec 29, 2020·2 cites·20 claims
- 1084US9881870B2Semiconductor device and manufacturing method thereofTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted Jan 30, 2018·3 cites·20 claims
- 1184US8765600B2Contact structure for reducing gate resistance and method of making the sameCHANG CHUNG-LONG·Filed 2010·Granted Jul 1, 2014·10 cites·20 claims
- 1284US5635037AMethod of texture by in-situ masking and etching for thin film magnetic recording mediumIND TECH RES INST·Filed 1993·Granted Jun 3, 1997·40 cites·15 claims
- 1383US11081445B2Semiconductor device comprising air gaps having different configurationsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Aug 3, 2021·2 cites·20 claims
- 1482US9793212B2Interconnect structures and methods of forming sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted Oct 17, 2017·4 cites·20 claims
- 1581US10522396B1Methods of fabricating integrated circuit devices having reduced line end spacesTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Granted Dec 31, 2019·4 cites·20 claims
- 1677US6577149B2Method and device for addressable failure site test structureTAIWAN SEMICONDUCTOR MFG·Filed 2001·Granted Jun 10, 2003·27 cites·6 claims
- 1776US12243826B2Method for manufacturing semiconductor structure having raised via contactsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Mar 4, 2025·0 cites·20 claims
- 1876US2025157938A1Semiconductor structure having raised via contactsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 1973US11355436B2Semiconductor device and manufacturing method thereofTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Jun 7, 2022·0 cites·20 claims
- 2071US11676895B2Semiconductor device comprising air gaps having different configurationsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Jun 13, 2023·0 cites·20 claims
- 2168US10521537B2Method and system of generating layoutTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Granted Dec 31, 2019·1 cites·19 claims
- 2264US10847418B2Formation method of damascene structureTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Nov 24, 2020·0 cites·20 claims
- 2361US9892221B2Method and system of generating a layout including a fuse layout patternTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2014·Granted Feb 13, 2018·1 cites·20 claims
- 2460US10872806B2Semiconductor device and manufacturing method thereofTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Granted Dec 22, 2020·0 cites·20 claims
- 2558US2025142881A1Semiconductor structure including bottom isolation and method for manufacturing the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Application pending·0 cites
- 2658US2025364412A1Structure for self-aligned via and method for forming the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Application pending·0 cites
- 2757US10361156B2Semiconductor device and manufacturing method thereofTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Jul 23, 2019·0 cites·20 claims
- 2856US10170355B2Semiconductor device and manufacturing method thereofTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Jan 1, 2019·0 cites·20 claims
- 2956US9721836B2Structure and formation method of damascene structureTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted Aug 1, 2017·0 cites·20 claims
- 3055US8971014B2Protection structure for metal-oxide-metal capacitorHUA WEI-CHUN·Filed 2011·Granted Mar 3, 2015·1 cites·20 claims
- 3154US9711391B1Semiconductor device and manufacturing method thereofTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted Jul 18, 2017·0 cites·20 claims
- 3254US2024266216A1Metal structures with seamsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Application pending·0 cites
- 3352US9437485B2Method for line stress reduction through dummy shoulder structuresTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2014·Granted Sep 6, 2016·0 cites·20 claims
- 3451US10068836B2Metal gate transistor, integrated circuits, systems, and fabrication methods thereofTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Sep 4, 2018·0 cites·20 claims
- 3548US7135406B2Method for damascene formation using plug materials having varied etching ratesTAIWAN SEMICONDUCTOR MFG·Filed 2004·Granted Nov 14, 2006·4 cites·28 claims
- 3647US8450200B2Method for stacked contact with low aspect ratioYU CHEN-HUA·Filed 2010·Granted May 28, 2013·0 cites·20 claims
- 3745US10102972B2Method of forming capacitor structureTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted Oct 16, 2018·0 cites·20 claims
- 3845US9620421B2Metal gate transistor, integrated circuits, systems, and fabrication methods thereofHO CHIEN-CHIH·Filed 2010·Granted Apr 11, 2017·0 cites·21 claims
- 3945US2010213569A1Integrated circuits having fuses and systems thereofTAIWAN SEMICONDUCTOR MFG·Filed 2009·Application pending·0 cites
- 4042US8692351B2Dummy shoulder structure for line stress reductionKUO CHENG CHENG·Filed 2010·Granted Apr 8, 2014·0 cites·20 claims
- 4141US11348828B2Interconnect structure and method of forming the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Granted May 31, 2022·0 cites·20 claims
- 4235US6017821AChemical-mechanical polishing method for forming plugsWINBOND ELECTRONICS CORP·Filed 1997·Granted Jan 25, 2000·5 cites·13 claims
Join the waitlist — get patent alerts
Get an alert when Jye-Yen Cheng files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →