Inventor · disambiguated record
Jyuh-Fuh Lin
Also filed as: LIN JYUH-FUH
11 granted patents·66 citations·filing 2012–2019
89Inventor score
Top patents by PatentIndex Score
11 records- 0195US9594862B2Method of fabricating an integrated circuit with non-printable dummy featuresTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2014·Granted Mar 14, 2017·19 cites·16 claims
- 0290US9436788B2Method of fabricating an integrated circuit with block dummy for optimized pattern density uniformityTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2014·Granted Sep 6, 2016·11 cites·19 claims
- 0390US9436787B2Method of fabricating an integrated circuit with optimized pattern density uniformityTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2014·Granted Sep 6, 2016·11 cites·20 claims
- 0489US11061317B2Method of fabricating an integrated circuit with non-printable dummy featuresTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Jul 13, 2021·4 cites·20 claims
- 0587US10170276B2Method of fabricating an integrated circuit with a pattern density-outlier-treatment for optimized pattern density uniformityTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Jan 1, 2019·3 cites·20 claims
- 0686US8755045B2Detecting method for forming semiconductor deviceLIN JYUH-FUH·Filed 2012·Granted Jun 17, 2014·15 cites·19 claims
- 0780US10811225B2Method of fabricating an integrated circuit with a pattern density-outlier-treatment for optimized pattern density uniformityTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Oct 20, 2020·1 cites·20 claims
- 0879US10431423B2Method of fabricating an integrated circuit with a pattern density-outlier-treatment for optimized pattern density uniformityTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Granted Oct 1, 2019·1 cites·20 claims
- 0970US10359695B2Method of fabricating an integrated circuit with non-printable dummy featuresTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Jul 23, 2019·1 cites·20 claims
- 1060US9552964B2Method of fabricating an integrated circuit with a pattern density-outlier-treatment for optimized pattern density uniformityTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2014·Granted Jan 24, 2017·0 cites·21 claims
- 1154US9658538B2System and technique for rasterizing circuit layout dataTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2014·Granted May 23, 2017·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →