Inventor · disambiguated record
Kanad Chakraborty
Also filed as: CHAKRABORTY KANAD
8 granted patents·2 pending applications·80 citations·filing 2000–2015
86Inventor score
Top patents by PatentIndex Score
10 records- 0193US9618579B2Programmable circuits for correcting scan-test circuitry defects in integrated circuit designsLATTICE SEMICONDUCTOR CORP·Filed 2015·Granted Apr 11, 2017·10 cites·16 claims
- 0283US7511535B2Fine-grained power management of synchronous and asynchronous datapath circuitsAGERE SYSTEMS INC·Filed 2007·Granted Mar 31, 2009·15 cites·19 claims
- 0377US8977917B2Highly secure and extensive scan testing of integrated circuitsLATTICE SEMICONDUCTOR CORP·Filed 2013·Granted Mar 10, 2015·3 cites·20 claims
- 0477US7047163B1Method and apparatus for applying fine-grained transforms during placement synthesis interactionIBM·Filed 2000·Granted May 16, 2006·25 cites·12 claims
- 0562US9530486B1Adaptive technique for adjusting signal development across bit lines for read operation robustness in memory circuitsLATTICE SEMICONDUCTOR CORP·Filed 2015·Granted Dec 27, 2016·2 cites·14 claims
- 0662US7409659B2System and method for suppressing crosstalk glitch in digital circuitsAGERE SYSTEMS INC·Filed 2004·Granted Aug 5, 2008·13 cites·12 claims
- 0761US6532578B2Method of configuring integrated circuits using greedy algorithm for partitioning of N points in P isothetic rectanglesIBM·Filed 2001·Granted Mar 11, 2003·9 cites·23 claims
- 0857US9728273B2Embedded memory testing using back-to-back write/read operationsLATTICE SEMICONDUCTOR CORP·Filed 2014·Granted Aug 8, 2017·3 cites·10 claims
- 0934US2007194453A1Integrated circuit architecture for reducing interconnect parasiticsCHAKRABORTY KANAD·Filed 2006·Application pending·0 cites
- 1029US2015310933A1Configurable Test Address And Data Generation For Multimode Memory Built-In Self-TestingLATTICE SEMICONDUCTOR CORP·Filed 2014·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →