Inventor · disambiguated record
Kamal Chaudhary
Also filed as: CHAUDHARY KAMAL
35 granted patents·2,495 citations·filing 1995–2012
98Inventor score
Files withXILINX INC29NIJSSEN RAYMOND2ACHRONIX SEMICONDUCTOR CORP1MANOHAR RAJIT1SRINIVASAN SANKARANARAYANAN1
Top patents by PatentIndex Score
35 records- 0199US6448808B2Interconnect structure for a programmable logic deviceXILINX INC·Filed 2001·Granted Sep 10, 2002·225 cites·23 claims
- 0299US5914616AFPGA repeatable interconnect structure with hierarchical interconnect linesXILINX INC·Filed 1997·Granted Jun 22, 1999·495 cites·39 claims
- 0398US7075333B1Programmable circuit optionally configurable as a lookup table or a wide multiplexerXILINX INC·Filed 2004·Granted Jul 11, 2006·159 cites·22 claims
- 0498US5889411AFPGA having logic element carry chains capable of generating wide XOR functionsXILINX INC·Filed 1997·Granted Mar 30, 1999·279 cites·5 claims
- 0597US5963050AConfigurable logic element with fast feedback pathsXILINX INC·Filed 1997·Granted Oct 5, 1999·129 cites·13 claims
- 0696US5936424AHigh speed bus with tree structure for selecting bus driverXILINX INC·Filed 1997·Granted Aug 10, 1999·128 cites·13 claims
- 0796US5920202AConfigurable logic element with ability to evaluate five and six input functionsXILINX INC·Filed 1997·Granted Jul 6, 1999·121 cites·11 claims
- 0894US6204690B1FPGA architecture with offset interconnect linesXILINX INC·Filed 2000·Granted Mar 20, 2001·45 cites·11 claims
- 0994US6086631APost-placement residual overlap removal method for core-based PLD programming processXILINX INC·Filed 1998·Granted Jul 11, 2000·242 cites·20 claims
- 1093US5942913AFPGA repeatable interconnect structure with bidirectional and unidirectional interconnect linesXILINX INC·Filed 1997·Granted Aug 24, 1999·91 cites·9 claims
- 1191US6292022B2Interconnect structure for a programmable logic deviceXILINX INC·Filed 2001·Granted Sep 18, 2001·31 cites·23 claims
- 1291US6124731AConfigurable logic element with ability to evaluate wide logic functionsXILINX INC·Filed 2000·Granted Sep 26, 2000·37 cites·6 claims
- 1391US5596743AField programmable logic device with dynamic interconnections to a dynamic logic coreUNIV CALIFORNIA·Filed 1995·Granted Jan 21, 1997·162 cites·16 claims
- 1488US7932746B1One phase logicACHRONIX SEMICONDUCTOR CORP·Filed 2010·Granted Apr 26, 2011·7 cites·20 claims
- 1588US6051992AConfigurable logic element with ability to evaluate five and six input functionsXILINX INC·Filed 1999·Granted Apr 18, 2000·44 cites·4 claims
- 1685US8106683B2One phase logicNIJSSEN RAYMOND·Filed 2011·Granted Jan 31, 2012·6 cites·20 claims
- 1782US7536661B1Incremental placement during physical synthesisXILINX INC·Filed 2006·Granted May 19, 2009·12 cites·14 claims
- 1881US6362648B1Multiplexer for implementing logic functions in a programmable logic deviceXILINX INC·Filed 2000·Granted Mar 26, 2002·19 cites·35 claims
- 1978US8010923B1Latch based optimization during implementation of circuit designs for programmable logic devicesXILINX INC·Filed 2008·Granted Aug 30, 2011·7 cites·16 claims
- 2078US7428718B1Enhanced incremental placement during physical synthesisXILINX INC·Filed 2006·Granted Sep 23, 2008·9 cites·16 claims
- 2175US8593176B2One phase logicNIJSSEN RAYMOND·Filed 2012·Granted Nov 26, 2013·3 cites·20 claims
- 2275US5677638AHigh speed tristate bus with multiplexers for selecting bus driverXILINX INC·Filed 1996·Granted Oct 14, 1997·28 cites·7 claims
- 2374US7111214B1Circuits and methods for testing programmable logic devices using lookup tables and carry chainsXILINX INC·Filed 2002·Granted Sep 19, 2006·20 cites·40 claims
- 2472US6336208B1Delay optimized mapping for programmable gate arrays with multiple sized lookup tablesXILINX INC·Filed 1999·Granted Jan 1, 2002·60 cites·19 claims
- 2570US6201410B1Wide logic gate implemented in an FPGA configurable logic elementXILINX INC·Filed 1999·Granted Mar 13, 2001·20 cites·33 claims
- 2668US7072815B1Relocation of components for post-placement optimizationXILINX INC·Filed 2002·Granted Jul 4, 2006·14 cites·24 claims
- 2766US7146590B1Congestion estimation for programmable logic devicesXILINX INC·Filed 2004·Granted Dec 5, 2006·10 cites·25 claims
- 2865US6484298B1Method and apparatus for automatic timing-driven implementation of a circuit designXILINX INC·Filed 2000·Granted Nov 19, 2002·11 cites·20 claims
- 2963US8191019B2Non-predicated to predicated conversion of asynchronous representationsMANOHAR RAJIT·Filed 2009·Granted May 29, 2012·2 cites·29 claims
- 3063US7853914B1Fanout-optimization during physical synthesis for placed circuit designsXILINX INC·Filed 2007·Granted Dec 14, 2010·3 cites·14 claims
- 3163US6415425B1Method for analytical placement of cells using density surface representationsXILINX INC·Filed 1999·Granted Jul 2, 2002·38 cites·14 claims
- 3261US7590960B1Placing partitioned circuit designs within iterative implementation flowsXILINX INC·Filed 2007·Granted Sep 15, 2009·3 cites·19 claims
- 3357US6081914AMethod for implementing priority encoders using FPGA carry logicXILINX INC·Filed 1998·Granted Jun 27, 2000·32 cites·21 claims
- 3453US7058915B1Pin reordering during placement of circuit designsXILINX INC·Filed 2003·Granted Jun 6, 2006·3 cites·28 claims
- 3548US8146041B1Latch based optimization during implementation of circuit designs for programmable logic devicesSRINIVASAN SANKARANARAYANAN·Filed 2011·Granted Mar 27, 2012·0 cites·10 claims
Join the waitlist — get patent alerts
Get an alert when Kamal Chaudhary files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →