Inventor · disambiguated record
Kai Loon Cheong
Also filed as: CHEONG KAI LOON
4 granted patents·4 pending applications·2 citations·filing 2017–2023
61Inventor score
Files withINTEL CORP8
Top patents by PatentIndex Score
8 records- 0180US12453115B2Nanowire transistor structure and method of shapingINTEL CORP·Filed 2023·Granted Oct 21, 2025·0 cites·17 claims
- 0278US11869891B2Non-planar integrated circuit structures having mitigated source or drain etch from replacement gate processINTEL CORP·Filed 2018·Granted Jan 9, 2024·2 cites·6 claims
- 0376US12302632B2Non-planar integrated circuit structures having mitigated source or drain etch from replacement gate processINTEL CORP·Filed 2023·Granted May 13, 2025·0 cites·20 claims
- 0457US11869973B2Nanowire transistor structure and method of shapingINTEL CORP·Filed 2018·Granted Jan 9, 2024·0 cites·15 claims
- 0552US2025006737A1Stacked cmos transistor structures with complementary channel materialsINTEL CORP·Filed 2023·Application pending·0 cites
- 0647US2024332379A1Backside contact etch before cavity spacer formation for backside contact of transistor source/drainINTEL CORP·Filed 2023·Application pending·0 cites
- 0747US2024006499A1Gate spacer in stacked gate-all-around (gaa) device architectureINTEL CORP·Filed 2022·Application pending·0 cites
- 0834US2020161440A1Metal to source/drain contact area using thin nucleation layer and sacrificial epitaxial filmINTEL CORP·Filed 2017·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →