Inventor · disambiguated record
Kar Keng Chua
Also filed as: CHUA KAR KENG
30 granted patents·212 citations·filing 2001–2013
97Inventor score
Top patents by PatentIndex Score
30 records- 0187US7978493B1Data encoding scheme to reduce sense currentALTERA CORP·Filed 2008·Granted Jul 12, 2011·19 cites·10 claims
- 0286US7733121B2Methods and apparatus for programmably powering down structured application-specific integrated circuitsALTERA CORP·Filed 2007·Granted Jun 8, 2010·12 cites·23 claims
- 0386US7243315B2Methods for producing structured application-specific integrated circuits that are equivalent to field-programmable gate arraysALTERA CORP·Filed 2005·Granted Jul 10, 2007·18 cites·16 claims
- 0485US7243329B2Application-specific integrated circuit equivalents of programmable logic and associated methodsALTERA CORP·Filed 2004·Granted Jul 10, 2007·20 cites·18 claims
- 0585US7164289B1Real time feedback compensation of programmable logic memoryALTERA CORP·Filed 2005·Granted Jan 16, 2007·11 cites·12 claims
- 0683US8352899B1Method to modify an integrated circuit (IC) designALTERA CORP·Filed 2010·Granted Jan 8, 2013·12 cites·21 claims
- 0781US8327199B1Integrated circuit with configurable test pinsDASTIDAR JAYABRATA GHOSH·Filed 2010·Granted Dec 4, 2012·7 cites·20 claims
- 0880US7246339B2Methods for creating and expanding libraries of structured ASIC logic and other functionsALTERA CORP·Filed 2005·Granted Jul 17, 2007·11 cites·14 claims
- 0979US8533250B1Multiplier with built-in accumulatorFOO KOK YOONG·Filed 2009·Granted Sep 10, 2013·18 cites·20 claims
- 1079US8037377B1Techniques for performing built-in self-test of receiver channel having a serializerALTERA CORP·Filed 2008·Granted Oct 11, 2011·10 cites·22 claims
- 1178US8189362B2Data encoding scheme to reduce sense currentTAN JUN PIN·Filed 2011·Granted May 29, 2012·6 cites·17 claims
- 1277US7882408B1Real time feedback compensation of programmable logic memoryALTERA CORP·Filed 2006·Granted Feb 1, 2011·7 cites·22 claims
- 1376US7304497B2Methods and apparatus for programmably powering down structured application-specific integrated circuitsALTERA CORP·Filed 2005·Granted Dec 4, 2007·7 cites·14 claims
- 1475US7404169B2Clock signal networks for structured ASIC devicesALTERA CORP·Filed 2005·Granted Jul 22, 2008·7 cites·14 claims
- 1572US8863061B2Application-specific integrated circuit equivalents of programmable logic and associated methodsALTERA CORP·Filed 2013·Granted Oct 14, 2014·2 cites·20 claims
- 1672US6599764B1Isolation testing scheme for multi-die packagesALTERA CORP·Filed 2001·Granted Jul 29, 2003·18 cites·20 claims
- 1767US8261141B1Real time feedback compensation of programmable logic memoryCHOE KOK HENG·Filed 2011·Granted Sep 4, 2012·2 cites·26 claims
- 1866US7870513B2Application-specific integrated circuit equivalents of programmable logic and associated methodsALTERA CORP·Filed 2007·Granted Jan 11, 2011·3 cites·12 claims
- 1964US8786308B1Method and apparatus for providing signal routing controlALTERA CORP·Filed 2012·Granted Jul 22, 2014·2 cites·20 claims
- 2064US7363596B1Methods for storing and naming static library cells for lookup by logic synthesis and the likeALTERA CORP·Filed 2005·Granted Apr 22, 2008·4 cites·7 claims
- 2160US8694944B1Predicting routability of integrated circuitsSOO SZE HUEY·Filed 2009·Granted Apr 8, 2014·4 cites·23 claims
- 2256US8151224B1Method of designing integrated circuits including providing an option to select a mask layer setANG BOON JIN·Filed 2008·Granted Apr 3, 2012·2 cites·16 claims
- 2355US7586327B1Distributed memory circuitry on structured application-specific integrated circuit devicesALTERA CORP·Filed 2008·Granted Sep 8, 2009·2 cites·20 claims
- 2455US7071731B1Programmable Logic with Pipelined Memory OperationALTERA CORP·Filed 2005·Granted Jul 4, 2006·3 cites·20 claims
- 2554US9225335B2Clock signal networks for structured ASIC devicesALTERA CORP·Filed 2013·Granted Dec 29, 2015·0 cites·19 claims
- 2648US8595658B2Clock signal networks for structured ASIC devicesLIM CHOOI PEI·Filed 2008·Granted Nov 26, 2013·0 cites·24 claims
- 2748US7046566B1Voltage-based timing control of memory bit linesALTERA CORP·Filed 2004·Granted May 16, 2006·5 cites·20 claims
- 2844US8504963B2Application-specific integrated circuit equivalents of programmable logic and associated methodsCHUA KAR KENG·Filed 2012·Granted Aug 6, 2013·0 cites·16 claims
- 2941US8291355B2Application-specific integrated circuit equivalents of programmable logic and associated methodsCHUA KAR KENG·Filed 2010·Granted Oct 16, 2012·0 cites·20 claims
- 3040US7683689B1Delay circuit with delay cells in different orientationsALTERA CORP·Filed 2008·Granted Mar 23, 2010·0 cites·21 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →