Inventor · disambiguated record
Kannanthodath V. Jayakumar
Also filed as: JAYAKUMAR KANNANTHODATH V
7 granted patents·2 pending applications·35 citations·filing 2018–2024
82Inventor score
Top patents by PatentIndex Score
9 records- 0191US11018679B1On-chip phase-locked loop response measurementSILICON LAB INC·Filed 2019·Granted May 25, 2021·11 cites·19 claims
- 0289US11764913B2Jitter self-test using timestampsSKYWORKS SOLUTIONS INC·Filed 2022·Granted Sep 19, 2023·2 cites·16 claims
- 0389US10608649B1Relative frequency offset error and phase error detection for clocksSILICON LAB INC·Filed 2018·Granted Mar 31, 2020·12 cites·18 claims
- 0488US11228403B2Jitter self-test using timestampsSILICON LAB INC·Filed 2019·Granted Jan 18, 2022·3 cites·20 claims
- 0587US12166494B2Modified control loop in a digital phase-locked loopSKYWORKS SOLUTIONS INC·Filed 2022·Granted Dec 10, 2024·2 cites·19 claims
- 0685US12191866B2Linear prediction to suppress spurs in a digital phase-locked loopSKYWORKS SOLUTIONS INC·Filed 2022·Granted Jan 7, 2025·1 cites·24 claims
- 0780US10819354B2Accurate and reliable digital PLL lock indicatorSILICON LAB INC·Filed 2019·Granted Oct 27, 2020·4 cites·21 claims
- 0869US2025211241A1Linear prediction to suppress spurs in a digital phase-locked loopSKYWORKS SOLUTIONS INC·Filed 2024·Application pending·0 cites
- 0967US2025158624A1Modified control loop in a digital phase-locked loopSKYWORKS SOLUTIONS INC·Filed 2024·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →