Inventor · disambiguated record
Karan Kacker
Also filed as: KACKER KARAN
9 granted patents·1 pending application·52 citations·filing 2007–2015
84Inventor score
Files withKACKER KARAN6GEORGIA TECH RES INST1IBM1MICROSOFT TECHNOLOGY LICENSING LLC1SITARAMAN SURESH K1
Top patents by PatentIndex Score
10 records- 0196US8522430B2Clustered stacked vias for reliable electronic substratesKACKER KARAN·Filed 2012·Granted Sep 3, 2013·37 cites·8 claims
- 0288US10591979B2Battery management in a device with multiple batteriesMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2015·Granted Mar 17, 2020·8 cites·20 claims
- 0369US8242593B2Clustered stacked vias for reliable electronic substratesKACKER KARAN·Filed 2008·Granted Aug 14, 2012·4 cites·8 claims
- 0460US8382489B2Compliant off-chip interconnects for use in electronic packages and fabrication methodsGEORGIA TECH RES INST·Filed 2012·Granted Feb 26, 2013·1 cites·11 claims
- 0557US9099458B2Construction of reliable stacked via in electronic substrates—vertical stiffness control methodKACKER KARAN·Filed 2012·Granted Aug 4, 2015·0 cites·13 claims
- 0657US8866026B2Construction of reliable stacked via in electronic substrates—vertical stiffness control methodKACKER KARAN·Filed 2012·Granted Oct 21, 2014·0 cites·11 claims
- 0755US8258410B2Construction of reliable stacked via in electronic substrates—vertical stiffness control methodKACKER KARAN·Filed 2008·Granted Sep 4, 2012·0 cites·4 claims
- 0855US8206160B2Compliant off-chip interconnects for use in electronic packagesKACKER KARAN·Filed 2008·Granted Jun 26, 2012·1 cites·15 claims
- 0949US8766449B2Variable interconnect geometry for electronic packages and fabrication methodsSITARAMAN SURESH K·Filed 2007·Granted Jul 1, 2014·1 cites·6 claims
- 1045US2009189289A1Embedded constrainer discs for reliable stacked vias in electronic substratesIBM·Filed 2008·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →