Inventor · disambiguated record
Kan Wae Lam
Also filed as: LAM KAN WAE
10 granted patents·9 pending applications·36 citations·filing 2013–2025
85Inventor score
Top patents by PatentIndex Score
19 records- 0189US9391007B1Built-up lead frame QFN and DFN packages and method of making thereofNXP BV·Filed 2015·Granted Jul 12, 2016·10 cites·10 claims
- 0286US10410941B2Wafer level semiconductor device with wettable flanksNexperia BV·Filed 2016·Granted Sep 10, 2019·6 cites·18 claims
- 0386US9640463B2Built-up lead frame package and method of making thereofNexperia BV·Filed 2015·Granted May 2, 2017·7 cites·7 claims
- 0480US9847283B1Semiconductor device with wettable corner leadsNexperia BV·Filed 2016·Granted Dec 19, 2017·6 cites·14 claims
- 0575US11227820B2Through hole side wettable flankNexperia BV·Filed 2020·Granted Jan 18, 2022·1 cites·20 claims
- 0671US10304759B2Electronic device and method of making sameNexperia BV·Filed 2016·Granted May 28, 2019·2 cites·4 claims
- 0767US9269690B2Packaged semiconductor device with interior polygonal padsNXP BV·Filed 2013·Granted Feb 23, 2016·3 cites·16 claims
- 0861US10262926B2Reversible semiconductor dieNexperia BV·Filed 2016·Granted Apr 16, 2019·1 cites·13 claims
- 0959US2025174526A1Semiconductor packageNexperia BV·Filed 2024·Application pending·0 cites
- 1056US2025006597A1Semiconductor device as well as a method for manufacturing such semiconductor deviceNexperia BV·Filed 2024·Application pending·0 cites
- 1152US2025385190A1Package comprising a first and a second semiconductor die, wherein a galvanic coupling is provided between those semiconductor dies, as well as a corresponding methodNexperia BV·Filed 2025·Application pending·0 cites
- 1252US2025385194A1Leadless package comprising a first and a second semiconductor die, wherein a galvanic isolation is provided between those semiconductor dies, as well as a corresponding methodNexperia BV·Filed 2025·Application pending·0 cites
- 1352US2025385188A1Leadless package comprising a first and a second semiconductor die, wherein a galvanic coupling is provided between those semiconductor dies, as well as a corresponding methodNexperia BV·Filed 2025·Application pending·0 cites
- 1452US2024105514A1Method of singulation of dies from a waferNexperia BV·Filed 2023·Application pending·0 cites
- 1552US2025385193A1A leadless package comprising a first and a second semiconductor die, wherein a galvanic coupling is provided between those semiconductor dies, as well as a corresponding methodNexperia BV·Filed 2025·Application pending·0 cites
- 1650US2023178507A1Step interconnect metallization to enable panel level packagingNexperia BV·Filed 2022·Application pending·0 cites
- 1741US10056343B2Packaged semiconductor device with interior polygonal padsNexperia BV·Filed 2016·Granted Aug 21, 2018·0 cites·10 claims
- 1834US10256168B2Semiconductor device and lead frame thereforNexperia BV·Filed 2016·Granted Apr 9, 2019·0 cites·19 claims
- 1934US2017170103A1Electronic device and manufacturing method thereforNexperia BV·Filed 2016·Application pending·0 cites
Join the waitlist — get patent alerts
Get an alert when Kan Wae Lam files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →