Inventor · disambiguated record
Kavitha Nagarajan
Also filed as: NAGARAJAN KAVITHA
1 granted patent·18 pending applications·0 citations·filing 2022–2023
9Inventor score
Files withINTEL CORP19
Top patents by PatentIndex Score
19 records- 0156US12504797B2Thermal management systems for electronic devices and related methodsINTEL CORP·Filed 2022·Granted Dec 23, 2025·0 cites·21 claims
- 0254US2025113428A1Technologies for an electromagnetic interference shieldINTEL CORP·Filed 2023·Application pending·0 cites
- 0353US2025054819A1Stiffener assembly and method for making a semiconductor assemblyINTEL CORP·Filed 2023·Application pending·0 cites
- 0452US2025008685A1Fan modules for electronic devicesINTEL CORP·Filed 2023·Application pending·0 cites
- 0552US2025052512A1Multi-sectional vapor chambersINTEL CORP·Filed 2023·Application pending·0 cites
- 0651US2024332251A1Dummy silicon stiffening mechanism for module warpage mitigationINTEL CORP·Filed 2023·Application pending·0 cites
- 0747US2024234303A9Integrated inductor over transistor layerINTEL CORP·Filed 2022·Application pending·0 cites
- 0847US2024234234A9Copper fill for heat management in integrated circuit deviceINTEL CORP·Filed 2022·Application pending·0 cites
- 0947US2023395524A1Emi cage for microstrip routing via dual layer underfill conceptINTEL CORP·Filed 2022·Application pending·0 cites
- 1046US2023395578A1Memory package on extended base die over soc die for package layer count and form factor reductionINTEL CORP·Filed 2022·Application pending·0 cites
- 1146US2023420354A1Electrical conductor extending from a surface of a substrateINTEL CORP·Filed 2022·Application pending·0 cites
- 1246US2023420384A1Slotted stiffener for a package substrateINTEL CORP·Filed 2022·Application pending·0 cites
- 1346US2023395576A1Memory on package (mop) architectureINTEL CORP·Filed 2022·Application pending·0 cites
- 1446US2023420350A1Hyper density package substrate and memory coupled to a modified semi-additive process boardINTEL CORP·Filed 2022·Application pending·0 cites
- 1546US2023395493A1On package interconnect architecture for high-speed memoryINTEL CORP·Filed 2022·Application pending·0 cites
- 1646US2023420345A1Copper rings for bga count reduction in small form factor packagesINTEL CORP·Filed 2022·Application pending·0 cites
- 1746US2023395577A1Soc-memory integration to achieve smallest and thinnest memory on package architectureINTEL CORP·Filed 2022·Application pending·0 cites
- 1846US2023397333A1Ultra-laser though hole (ulth) by multi-stacked core conceptINTEL CORP·Filed 2022·Application pending·0 cites
- 1943US2025004044A1Apparatus and method for detecting warpage in an electronic systemINTEL CORP·Filed 2023·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →