Inventor · disambiguated record
Kaushik Popat
Also filed as: POPAT KAUSHIK · POPAT KAUSHIK L
15 granted patents·749 citations·filing 1988–2014
95Inventor score
Top patents by PatentIndex Score
15 records- 0194US7191318B2Native copy instruction for file-access processor with copy-rule-based validationALACRITECH INC·Filed 2003·Granted Mar 13, 2007·142 cites·21 claims
- 0294US4868522AClock signal distribution deviceGAZELLE MICROCIRCUITS INC·Filed 1988·Granted Sep 19, 1989·94 cites·19 claims
- 0392US5623672AArrangement and method of arbitration for a resource with shared user request signals and dynamic priority assignmentCIRRUS LOGIC INC·Filed 1994·Granted Apr 22, 1997·183 cites·39 claims
- 0490US6594716B2Mixed-signal single-chip integrated system electronics for data storage devicesCIRRUS LOGIC INC·Filed 2001·Granted Jul 15, 2003·24 cites·6 claims
- 0586US7475173B2Integrated disc drive controllerBROADCOM CORP·Filed 2006·Granted Jan 6, 2009·12 cites·21 claims
- 0681US7529869B2Mixed-signal single-chip integrated system electronics for data storage devicesBROADCOM CORP·Filed 2005·Granted May 5, 2009·3 cites·60 claims
- 0778US6480948B1Configurable system memory mapCIRRUS LOGIC INC·Filed 1999·Granted Nov 12, 2002·88 cites·14 claims
- 0878US6314480B1Mixed-signal single-chip integrated system electronics for magnetic hard disk drivesCIRRUS LOGIC INC·Filed 1999·Granted Nov 6, 2001·62 cites·15 claims
- 0978US5500611AIntegrated circuit with input/output pad having pullup or pulldownCIRRUS LOGIC INC·Filed 1994·Granted Mar 19, 1996·35 cites·15 claims
- 1062US5564114AMethod and an arrangement for handshaking on a bus to transfer information between devices in a computer systemCIRRUS LOGIC INC·Filed 1995·Granted Oct 8, 1996·48 cites·24 claims
- 1160US6618780B1Method and apparatus for controlling interrupt priority resolutionCIRRUS LOGIC INC·Filed 1999·Granted Sep 9, 2003·37 cites·13 claims
- 1254US8060674B2Systems and methods for data storage devices and controllersNEMAZIE SIAMACK·Filed 2009·Granted Nov 15, 2011·0 cites·49 claims
- 1345US9507729B2Method and processor for reducing code and latency of TLB maintenance operations in a configurable processorSYNOPSYS INC·Filed 2014·Granted Nov 29, 2016·0 cites·16 claims
- 1444US6374313B1FIFO and method of operating same which inhibits output transitions when the last cell is read or when the FIFO is erasedCIRRUS LOGIC INC·Filed 1994·Granted Apr 16, 2002·15 cites·6 claims
- 1540US5804990AWired combinational logic circuit with pullup and pulldown devicesCIRRUS LOGIC INC·Filed 1996·Granted Sep 8, 1998·6 cites·11 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →