Inventor · disambiguated record
Kameswar Subramaniam
Also filed as: SUBRAMANIAM KAMESWAR
10 granted patents·10 pending applications·19 citations·filing 2010–2025
81Inventor score
Technology areasG06F
Top patents by PatentIndex Score
20 records- 0185US9612930B2Providing autonomous self-testing of a processorINTEL CORP·Filed 2015·Granted Apr 4, 2017·5 cites·23 claims
- 0284US9052890B2Execute at commit state update instructions, apparatus, methods, and systemsPHILLIPS JAMES E·Filed 2010·Granted Jun 9, 2015·12 cites·21 claims
- 0376US2025315260A1System, apparatus and methods for performant read and write of processor state information responsive to list instructionsINTEL CORP·Filed 2025·Application pending·0 cites
- 0472US10620969B2System, apparatus and method for providing hardware feedback information in a processorINTEL CORP·Filed 2018·Granted Apr 14, 2020·1 cites·20 claims
- 0566US12327117B2System, apparatus and methods for performant read and write of processor state information responsive to list instructionsINTEL CORP·Filed 2021·Granted Jun 10, 2025·0 cites·18 claims
- 0660US9329865B2Context control and parameter passing within microcode based instruction routinesCOMBS JONATHAN D·Filed 2013·Granted May 3, 2016·1 cites·20 claims
- 0758US12235791B2Loop driven region based frontend translation control for performant and secure data-space guided micro-sequencingINTEL CORP·Filed 2021·Granted Feb 25, 2025·0 cites·25 claims
- 0851US2025306937A1Concurrent decode of complex instructions having varying numbers of decoded instructionsINTEL CORP·Filed 2024·Application pending·0 cites
- 0951US2024330053A1Region-aware memory bandwidth allocation controlINTEL CORP·Filed 2023·Application pending·0 cites
- 1046US2023195634A1Prefetcher with low-level software configurabilityINTEL CORP·Filed 2021·Application pending·0 cites
- 1145US8832419B2Enhanced microcode address stack pointer manipulationCOMBS JONATHAN D·Filed 2010·Granted Sep 9, 2014·0 cites·20 claims
- 1245US2024329993A1Instructions for write and/or read of control and/or status registersSUBRAMANIAM KAMESWAR·Filed 2023·Application pending·0 cites
- 1344US2023057623A1Issue, execution, and backend driven frontend translation control for performant and secure data-space guided micro-sequencingINTEL CORP·Filed 2021·Application pending·0 cites
- 1444US2024329992A1Support for a 32-bit immediate as indicated by an instruction prefixSUBRAMANIAM KAMESWAR·Filed 2023·Application pending·0 cites
- 1542US12373206B2Methods, systems, and apparatuses to optimize cross-lane packed data instruction implementation on a partial width processor with a minimal number of micro-operationsINTEL CORP·Filed 2020·Granted Jul 29, 2025·0 cites·18 claims
- 1642US11354128B2Optimized mode transitions through predicting target stateINTEL CORP·Filed 2015·Granted Jun 7, 2022·0 cites·23 claims
- 1742US2019205061A1Processor, method, and system for reducing latency in accessing remote registersINTEL CORP·Filed 2017·Application pending·0 cites
- 1838US2012079248A1Aliased Parameter Passing Between Microcode Callers and Microcode SubroutinesCOMBS JONATHAN D·Filed 2010·Application pending·0 cites
- 1937US2012079237A1Saving Values Corresponding to Parameters Passed Between Microcode Callers and Microcode Subroutines from Microcode Alias Locations to a Destination Storage LocationCOMBS JONATHAN D·Filed 2010·Application pending·0 cites
- 2033US8793469B2Programmable logic array and read-only memory area reduction using context-sensitive logic for data space manipulationSUBRAMANIAM KAMESWAR·Filed 2010·Granted Jul 29, 2014·0 cites·19 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →